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User’s Manual
Preliminary PPC440x5 CPU Core
intrupts.fm.
September 12, 2002
Page 191 of 589
Save/Restore Register 1 (SRR1)
Set to the contents of the MSR at the time of the interrupt.
Machine State Register (MSR)
CE, ME, DE Unchanged.
All other MSR bits set to 0.
6.5.10 Auxiliary Processor Unavailable Interrupt
An Auxiliary Processor Unavailable interrupt occurs when no higher priority exception exists, an attempt is
made to execute an auxiliary processor instruction which is not implemented within the PPC440x5 core but
which is recognized by an attached auxiliary processor, and auxiliary processor instruction processing is not
enabled. The enabling of auxiliary processor instruction processing is implementation-dependent. See the
user’s manual for the attached auxiliary processor.
When an Auxiliary Processor Unavailable interrupt occurs, the processor suppresses the execution of the
instruction causing the Auxiliary Processor Unavailable exception, the interrupt processing registers are
updated as indicated below (all registers not listed are unchanged), and instruction execution resumes at
address IVPR[IVP] || IVOR9[IVO] || 0b0000.
Save/Restore Register 0 (SRR0)
Set to the effective address of the next instruction causing the Auxiliary Processor Unavail-
able interrupt.
Save/Restore Register 1 (SRR1)
Set to the contents of the MSR at the time of the interrupt.
Machine State Register (MSR)
CE, ME, DE Unchanged.
All other MSR bits set to 0.
6.5.11 Decrementer Interrupt
A Decrementer interrupt occurs when no higher priority exception exists, a Decrementer exception exists
(TSR[DIS] = 1), and the interrupt is enabled (TCR[DIE] = 1 and MSR[EE] = 1). See Chapter 7, “Timer Facili-
ties” for more information on Decrementer exceptions.
Note: MSR[EE] also enables the External Input and Fixed-Interval Timer interrupts.
When a Decrementer interrupt occurs, the interrupt processing registers are updated as indicated below (all
registers not listed are unchanged), and instruction execution resumes at address IVPR[IVP] || IVOR10[IVO]
|| 0b0000.
Save/Restore Register 0 (SRR0)
Set to the effective address of the next instruction to be executed.