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dcbz
Data Cache Block Set to Zero
PPC440x5 CPU Core User’s Manual Preliminary
Page 302 of 589
instrset.fm.
September 12, 2002
dcbz
Data Cache Block Set to Zero
EA ← (RA|0) + (RB)
DCBZ(EA)
An effective address (EA) is formed by adding an index to a base address. The index is the contents of
register RB. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise.
If the data block at the EA is in the data cache and the memory page referenced by the EA is marked as
cacheable and non-write-through, the data in the cache block is set to 0 and marked as dirty (modified).
If the data block at the EA is not in the data cache and the memory page referenced by the EA is marked as
cacheable and non-write-through, a cache block is established and set to 0 and marked as dirty. Note that
nothing is read from main storage, as described in the programming note.
If the memory page referenced by the EA is marked as either write-through or as caching inhibited, an Align-
ment exception occurs.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
• None
Invalid Instruction Forms
• Reserved fields
Programming Notes
Because dcbz can establish an address in the data cache without copying the contents of that address from
main storage, the address established may be invalid with respect to the storage subsystem. A subsequent
operation may cause the address to be copied back to main storage, for example, to make room for a new
cache block; a Data Machine Check exception could occur under these circumstances.
If dcbz is attempted to an EA in a memory page which is marked as caching inhibited or as write-through, the
software alignment exception handler should emulate the instruction by storing zeros to the block referenced
by the EA. The store instructions in the emulation software will cause main storage to be updated (and
possibly the cache, if the EA is in a page marked as write-through).
Exceptions
An alignment exception occurs if the EA is marked as caching inhibited or as write-through.
This instruction is considered a “store” with respect to Data Storage exceptions. See Data Storage Interrupt
on page 181 for more information.
dcbz RA, RB
31 RA RB 1014
0 6 11 16 21 31