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User’s Manual
Preliminary PPC440x5 CPU Core
overview.fm.
September 12, 2002
Page 35 of 589
tion in real time. Debug wait mode enables the processor to continue to service real-time critical interrupts
while instruction execution is otherwise stopped for hardware debug. The debug modes are controlled by
Debug Control Register 0 (DBCR0) and the setting of bits in the Machine State Register (MSR).
Internal debug mode supports accessing architected processor resources, setting hardware and software
breakpoints, and monitoring processor status. In internal debug mode, debug events can generate debug
exceptions, which can interrupt normal program flow so that monitor software can collect processor status
and alter processor resources.
Internal debug mode relies on exception-handling software—running on the processor—along with an
external communications path to debug software problems. This mode is used while the processor continues
executing instructions and enables debugging of problems in application or operating system code. Access to
debugger software executing in the processor while in internal debug mode is through a communications port
on the processor board, such as a serial port or ethernet connection.
External debug mode supports stopping, starting, and single-stepping the processor, accessing architected
processor resources, setting hardware and software breakpoints, and monitoring processor status. In
external debug mode, debug events can architecturally “freeze” the processor. While the processor is frozen,
normal instruction execution stops, and the architected processor resources can be accessed and altered
using a debug tool (such as RISCWatch) attached through the JTAG port. This mode is useful for debugging
hardware and low-level control software problems.
1.3.6.2 Development Tool Support
The PPC440x5 provides powerful debug support for a wide range of hardware and software development
tools.
The OS Open real-time operating system debugger is an example of an operating system-aware debugger,
implemented using software traps.
RISCWatch is an example of a development tool that uses the external debug mode, debug events, and the
JTAG port to support hardware and software development and debugging.
The RISCTrace™ feature of RISCWatch is an example of a development tool that uses the real-time trace
capability of the PPC440x5.
1.4 Core Interfaces
Several interfaces to the PPC440x5 core support the IBM CoreConnect on-chip system architecture, which
simplifies the attachment of on-chip devices. These interfaces include:
• Processor local bus (PLB)
• Device configuration register (DCR) interface
• Auxiliary processor unit (APU) port
• JTAG, debug, and trace ports
• Interrupt interface
• Clock and power management interface
Several of these interfaces are described briefly in the sections below.