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isync
Instruction Synchronize
PPC440x5 CPU Core User’s Manual Preliminary
Page 320 of 589
instrset.fm.
September 12, 2002
isync
Instruction Synchronize
The isync instruction is a context synchronizing instruction.
isync provides an ordering function for the effects of all instructions executed by the processor. Executing
isync insures that all instructions preceding the isync instruction execute before isync completes, except
that storage accesses caused by those instructions need not have completed. Furthermore, all instructions
preceding the isync are guaranteed to be unaffected by any context changes initiated by instructions after
the isync.
No subsequent instructions are initiated by the processor until isync completes. Finally, execution of isync
causes the processor to discard any prefetched instructions (prefetched from the cache, not instructions that
are in the cache or on their way into the cache), with the effect that subsequent instructions are fetched and
executed in the context established by the instructions preceding isync.
isync causes any caching inhibited instruction fetches from memory to be aborted and any data associated
with them to be discarded. Cacheable instruction fetches from memory are not aborted however, as these
should be handled by the icbi instructions which must precede the isync if software wishes to invalidate any
cached instructions.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
• None
Invalid Instruction Forms
• Reserved fields
Programming Note
See the discussion of context synchronizing instructions in Synchronization on page 82.
The following code example illustrates the necessary steps for self-modifying code. This example assumes
that addr1 is both data and instruction cacheable.
stw regN, addr1 # data in regN is to become an instruction at addr1
dcbst addr1 # forces data from the data cache to memory
msync # wait until the data actually reaches the memory
icbi addr1 # invalidate the instruction if it is in the cache (or in the #
process of being fetched into the cache)
msync # wait until the icbi completes
isync # discard and refetch any instructions (including
# possibly the instruction at addr1) which may have
# already been fetched from the cache and be in the
# pipeline after the isync
isync
19 150
0 6 21 31