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User’s Manual
Preliminary PPC440x5 CPU Core
ppc440x5TOC.fm.
September 12, 2002
Page 5 of 583
2.10 Synchronization ............................................................................................................................. 82
2.10.1 Context Synchronization ...................................................................................................... 82
2.10.2 Execution Synchronization .................................................................................................. 83
2.10.3 Storage Ordering and Synchronization ............................................................................... 84
3. Initialization ............................................................................................................... 85
3.1 PPC440x5 Core State After Reset .................................................................................................. 85
3.2 Reset Types .................................................................................................................................. 89
3.3 Reset Sources ................................................................................................................................. 89
3.4 Initialization Software Requirements ............................................................................................... 89
4. Instruction and Data Caches ................................................................................... 95
4.1 Cache Array Organization and Operation ....................................................................................... 95
4.1.1 Cache Line Replacement Policy ............................................................................................ 96
4.1.2 Cache Locking and Transient Mechanism ............................................................................ 99
4.2 Instruction Cache Controller .......................................................................................................... 103
4.2.1 ICC Operations .................................................................................................................... 104
4.2.2 Speculative Prefetch Mechanism ........................................................................................ 105
4.2.3 Instruction Cache Coherency .............................................................................................. 106
4.2.3.1 Self-Modifying Code ..................................................................................................... 106
4.2.3.2 Instruction Cache Synonyms ........................................................................................ 107
4.2.4 Instruction Cache Control and Debug ................................................................................. 108
4.2.4.1 Instruction Cache Management and Debug Instruction Summary ............................... 108
4.2.4.2 Core Configuration Register 0 (CCR0) ......................................................................... 108
4.2.4.3 Core Configuration Register 1 (CCR1) ......................................................................... 110
4.2.4.4 icbt Operation ............................................................................................................... 111
4.2.4.5 icread Operation ........................................................................................................... 112
4.2.4.6 Instruction Cache Parity Operations ............................................................................. 114
4.2.4.7 Simulating Instruction Cache Parity Errors for Software Testing ................................. 114
4.3 Data Cache Controller ................................................................................................................... 115
4.3.1 DCC Operations .................................................................................................................. 116
4.3.1.1 Load and Store Alignment ............................................................................................ 117
4.3.1.2 Load Operations ........................................................................................................... 118
4.3.1.3 Store Operations .......................................................................................................... 119
4.3.1.4 Line Flush Operations .................................................................................................. 121
4.3.1.5 Data Read PLB Interface Requests ............................................................................. 122
4.3.1.6 Data Write PLB Interface Requests ............................................................................. 123
4.3.1.7 Storage Access Ordering ............................................................................................. 124
4.3.2 Data Cache Coherency ....................................................................................................... 124
4.3.3 Data Cache Control and Debug .......................................................................................... 125
4.3.3.1 Data Cache Management and Debug Instruction Summary ........................................ 125
4.3.3.2 Core Configuration Register 0 (CCR0) ......................................................................... 126
4.3.3.3 Core Configuration Register 1 (CCR1) ......................................................................... 126
4.3.3.4 dcbt and dcbtst Operation ............................................................................................ 126
4.3.3.5 dcread Operation .......................................................................................................... 127
4.3.3.6 Data Cache Parity Operations ...................................................................................... 129
4.3.3.7 Simulating Data Cache Parity Errors for Software Testing .......................................... 130
5. Memory Management ............................................................................................. 133