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CCR0 (cont.)
Core Configuration Register 0
Preliminary PPC440x5 CPU Core User’s Manual
regsumm440core.fm.
September 12, 2002 Page 461 of 589
23 FLSTA
Force Load/Store Alignment
0 No Alignment exception on integer storage
access instructions, regardless of alignment
1 An alignment exception occurs on integer
storage access instructions if data address is not
on an operand boundary.
See Load and Store Alignment on page 117.
24:27 Reserved
28:29 ICSLC Instruction Cache Speculative Line Count
Number of additional lines (0–3) to fill on instruc-
tion fetch miss.
See Speculative Prefetch Mechanism on
page 105.
30:31 ICSLT Instruction Cache Speculative Line Threshold
Number of doublewords that must have already
been filled in order that the current speculative
line fill is not abandoned on a redirection of the
instruction stream.
See Speculative Prefetch Mechanism on
page 105.