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User’s Manual
Preliminary PPC440x5 CPU Core
debug.fm.
September 12, 2002
Page 235 of 589
8.3.6 Return (RET) Debug Event
RET debug events occur when RET debug events are enabled (DBCR0[RET] = 1) and execution is
attempted of a return (rfi, rfci, or rfmci) instruction.
When operating in external debug mode or debug wait mode, the occurrence of a RET debug event is
recorded in DBSR[RET] and causes the instruction execution to be suppressed. The processor then enters
the stop state and ceases the processing of instructions. The program counter will contain the address of the
return instruction which caused the RET debug event. Similarly, when operating in internal debug mode with
Debug interrupts enabled (MSR[DE] = 1), the occurrence of a RET debug event is recorded in DBSR[RET]
and causes the instruction execution to be suppressed. A Debug interrupt will occur with CSRR0 set to the
address of the return instruction which caused the RET debug event.
When operating in internal debug mode (and not also in external debug mode nor debug wait mode) with
Debug interrupts disabled (MSR[DE] = 0), then RET debug events can occur only for rfi instructions, and not
for rfci or rfmci instructions. Since the rfci or rfmci instruction is typically used to return from a critical class
interrupt handler (including the Debug interrupt itself), and MSR[DE] is typically 0 at the time of the return, the
rfci or rfmci must not be allowed to cause a RET debug event under these conditions, or else it would not be
possible to return from the critical class interrupts.
For the rfi instruction only, if a RET debug event occurs under these conditions (internal debug mode
enabled, external debug mode and debug wait mode disabled, and MSR[DE] = 0), then DBSR[RET] is set,
along with the Imprecise Debug Event (IDE) field of the DBSR. The instruction execution is not suppressed,
as no Debug interrupt will occur immediately. Instead, instruction execution continues, and a Debug interrupt
will occur if and when MSR[DE] is set to 1, thereby enabling Debug interrupts, assuming software has not
cleared the RET debug event status from the DBSR in the meantime. Upon such a “delayed” interrupt, the
Debug interrupt handler software may query the DBSR[IDE] field to determine that the Debug interrupt has
occurred imprecisely.
When operating in trace mode, the occurrence of a RET debug event is simply recorded in DBSR[RET] and is
indicated over the trace interface, and instruction execution continues.
8.3.7 Instruction Complete (ICMP) Debug Event
ICMP debug events occur when ICMP debug events are enabled (DBCR0[ICMP] = 1) and the PPC440x5
completes the execution of any instruction.
When operating in external debug mode or debug wait mode, the occurrence of an ICMP debug event is
recorded in DBSR[ICMP] and causes the processor to enter the stop state and cease processing instructions.
The program counter will contain the address of the instruction which would have executed next, had the
ICMP debug event not occurred. Note that if the instruction whose completion caused the ICMP debug event
was a branch instruction (and the branch conditions were satisfied), then upon entering the stop state the
program counter will contain the target of the branch, and not the address of the instruction that is sequen-
tially after the branch. Similarly, if the ICMP debug event is caused by the execution of a return (rfi, rfci, or
rfmci) instruction, then upon entering the stop state the program counter will contain the address being
returned to, and not the address of the instruction which is sequentially after the return instruction.
When operating in internal debug mode with Debug interrupts enabled (MSR[DE] = 1), the occurrence of an
ICMP debug event is recorded in DBSR[ICMP] and a Debug interrupt will occur with CSRR0 set to the
address of the instruction which would have executed next, had the ICMP debug event not occurred. Note