Filter
Top Products
User’s Manual
PPC440x5 CPU Core Preliminary
Page 66 of 589
prgmodel.fm.
September 12, 2002
The PPC440x5 core combines the static prediction mechanism defined by PowerPC Book-E, together with a
dynamic branch prediction mechanism, in order to provide correct branch prediction as often as possible. The
dynamic branch prediction mechanism is an implementation optimization, and is not part of the architecture,
nor is it visible to the programming model. Appendix B, “PPC440x5 Core Compiler Optimizations,” provides
additional information on the dynamic branch prediction mechanism.
The static branch prediction mechanism enables software to designate the “preferred” branch prediction via
bits in the instruction encoding. The “default” static branch prediction for conditional branches is as follows:
Predict that the branch is to be taken if ((BO[0] ∧ BO[2]) ∨ s)= 1
where s is bit 16 of the instruction (the sign bit of the displacement for all bc forms, and zero for all bclr and
bcctr forms). In other words, conditional branches are predicted taken if they are “unconditional” (i.e., they do
not test the CR nor the CTR decrement, and are always taken), or if their branch displacement is “negative”
(i.e., the branch is branching “backwards” from the current instruction address). The standard prediction for
this case derives from considering the relative form of bc, often used at the end of loops to control the
number of times that a loop is executed. The branch is taken each time the loop is executed except the last,
so it is best if the branch is predicted taken. The branch target is the beginning of the loop, so the branch
displacement is negative and s = 1. Because this situation is most common, a branch is taken if s =1.
If branch displacements are positive, s = 0, then the branch is predicted not taken. Also, if the branch instruc-
tion is any form of bclr or bcctr except the “unconditional” form, then s = 0, and the branch is predicted not
taken.
There is a peculiar consequence of this prediction algorithm for the absolute forms of bc (bca and bcla). As
described in Branch Addressing on page 64, if s = 1, the branch target is in high memory. If s = 0, the branch
target is in low memory. Because these are absolute-addressing forms, there is no reason to treat high and
low memory differently. Nevertheless, for the high memory case the standard prediction is taken, and for the
low memory case the standard prediction is not taken.
Another bit in the BO field allows software further control over branch prediction. Specifically, BO[4] is the
prediction reversal bit. If BO[4] = 0, the default prediction is applied. If BO[4] = 1, the reverse of the default
prediction is applied. For the cases in Table 2-23 where BO[4] = y, software can reverse the default predic-
tion by setting y to 1. This should only be done when the default prediction is likely to be wrong. Note that for
the “branch always” condition, reversal of the default prediction is not allowed, as BO[4] is designated as z for
this case, meaning the bit must be set to 0 or the instruction form is invalid.
2.5.5 Branch Control Registers
There are three registers in the PPC440x5 which are associated with branch processing, and they are
described in the following sections.
2.5.5.1 Link Register (LR)
The LR is written from a GPR using mtspr, and can be read into a GPR using mfspr. The LR can also be
updated by the “link update” form of branch instructions (instruction field LK = 1). Such branch instructions
load the LR with the address of the instruction following the branch instruction (4 + address of the branch
instruction). Thus, the LR contents can be used as a return address for a subroutine that was entered using a
link update form of branch. The bclr instruction uses the LR in this fashion, enabling indirect branching to any
address.