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User’s Manual
PPC440x5 CPU Core Preliminary
Page 134 of 589
mmu.fm.
September 12, 2002
• Memory coherence required (M) storage attribute
Because the PPC440x5 does not provide hardware support for multiprocessor coherence, the memory
coherence required storage attribute has no effect. If a TLB entry is created with M=1, then any memory
transactions for the page associated with that TLB entry will be indicated as being memory coherence
required via a corresponding transfer attribute interface signal, but the setting will have no effect on the
operation within the PPC440x5 core.
• TLB Invalidate virtual address (tlbiva)instruction
The tlbiva instruction is used to support the invalidation of TLB entries in a multiprocessor environment
with hardware-enforced coherency, which is not supported by the PPC440x5. Consequently, the
attempted execution of this instruction will cause an Illegal Instruction exception type Program interrupt.
The tlbwe instruction may be used to invalidate TLB entries in a uniprocessor environment.
• TLB Synchronize (tlbsync) instruction
The tlbsync instruction is used to synchronize software TLB management operations in a multiprocessor
environment with hardware-enforced coherency, which is not supported by the PPC440x5. Conse-
quently, this instruction is treated as a no-op.
• Page Sizes
PowerPC Book-E defines sixteen different page sizes, but does not require that an implementation sup-
port all of them. Furthermore, some of the page sizes are only applicable to 64-bit implementations, as
they are larger than a 32-bit effective address space can support (4GB). Accordingly, the PPC440x5 sup-
ports eight of the sixteen page sizes, from 1KB up to 256MB, as mentioned above and as listed in Table
5-2 Page Size and Effective Address to EPN Comparison on page 140.
• Address Space
Since the PPC440x5 is a 32-bit implementation of the 64-bit PowerPC Book-E architecture, there are dif-
ferences in the sizes of some of the TLB fields. First, the Effective Page Number (EPN) field varies from
4 to 22 bits, depending on page size. Second, the page number portion of the real address is made up of
a concatenation of two TLB fields, rather than a single Real Page Number (RPN) field as described in
PowerPC Book-E. These fields are the RPN field (which can vary from 4 to 22 bits, depending on page
size), and the Extended Real Page Number (ERPN) field, which is 4 bits, for a total of 36 bits of real
address, when combined with the page offset portion of the real address. See Address Translation on
page 140 for a more detailed explanation of these fields and the formation of the real address.
5.2 Translation Lookaside Buffer
The Translation Lookaside Buffer (TLB) is the hardware resource that controls translation, protection, and
storage attributes. A single unified 64-entry, fully-associative TLB is used for both instruction and data
accesses. In addition, the PPC440x5 implements two separate, smaller “shadow” TLB arrays, one for instruc-
tion fetch accesses and one for data accesses. These shadow TLBs improve performance by lowering the
latency for address translation, and by reducing contention for the main unified TLB between instruction
fetching and data storage accesses. See Shadow TLB Arrays on page 151 for additional information on the
operation of the shadow TLB arrays.