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sc
System Call
PPC440x5 CPU Core User’s Manual Preliminary
Page 404 of 589
instrset.fm.
September 12, 2002
sc
System Call
SRR1 ← MSR
SRR0 ← 4 + address of sc instruction
PC ← IVPR
0:15
|| IVOR8
16:27
||
4
0
MSR[WE, EE, PR, FP, FE0, FE1, DWE, DS, IS] ←
9
0
A System Call exception is generated, and a System Call interrupt occurs (see System Call Interrupt on
page 190 for more information on System Call interrupts). The contents of the MSR are copied into SRR1
and (4 + address of
sc instruction) is placed into SRR0.
The program counter (PC) is then loaded with the interrupt vector address. The interrupt vector address is
formed by concatenating the high halfword of the Interrupt Vector Prefix Register (IVPR), bits 16:27 of the
Interrupt Vector Offset Register 8 (IVOR8), and 0b0000.
The MSR[WE, EE, PR, FP, FE0, FE1, DWE, DS, IS] bits are set to 0.
Program execution continues at the new address in the PC.
Registers Altered
• SRR0
• SRR1
• MSR[WE, EE, PR, FP, FE0, FE1, DWE, DS, IS]
Invalid Instruction Forms
• Reserved fields
Programming Note
Execution of this instruction is context-synchronizing (see Context Synchronization on page 82).
sc
17 1
06 30 31