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ICDBTRH
Instruction Cache Debug Tag Register High
PPC440x5 CPU Core User’s Manual Preliminary
Page 492 of 589
regsumm440core.fm.
September 12, 2002
ICDBTRH
SPR 0x39F Supervisor Read-Only
See icread Operation on page 112.
Figure 10-26. Instruction Cache Debug Tag Register High (ICDBTRH)
0:23 Tag Effective Address
Bits 0:23 of the 32-bit effective address associated
with the cache line read by icread.
24 V
Cache Line Valid
0 Cache line is not valid.
1 Cache line is valid.
The valid indicator for the cache line read by
icread.
25:26 TPAR Tag Parity
The parity bits for the address tag for the cache
line read by icread, if CCR0[CRPE] is set.
27 DAPAR Instruction Data parity
The parity bit for the instruction word at the 32-bit
effective address specified in the icread instruc-
tion, if CCR0[CRPE] is set.
28:31
Reserved
0 23 24 25 26 27 28 31
TEA
V
TPAR
DAPAR