Filter
Top Products
User’s Manual
PPC440x5 CPU Core Preliminary
Page 6 of 583
ppc440x5TOC.fm.
September 12, 2002
5.1 MMU Overview .............................................................................................................................. 133
5.1.1 Support for PowerPC Book-E MMU Architecture ................................................................ 133
5.2 Translation Lookaside Buffer ......................................................................................................... 134
5.3 Page Identification ......................................................................................................................... 138
5.3.1 Virtual Address Formation ................................................................................................... 138
5.3.2 Address Space Identifier Convention ................................................................................... 138
5.3.3 TLB Match Process .............................................................................................................. 139
5.4 Address Translation ...................................................................................................................... 140
5.5 Access Control .............................................................................................................................. 142
5.5.1 Execute Access ................................................................................................................... 142
5.5.2 Write Access ........................................................................................................................ 142
5.5.3 Read Access ........................................................................................................................ 143
5.5.4 Access Control Applied to Cache Management Instructions ............................................... 143
5.6 Storage Attributes .......................................................................................................................... 145
5.6.1 Write-Through (W) ............................................................................................................... 145
5.6.2 Caching Inhibited (I) ............................................................................................................. 145
5.6.3 Memory Coherence Required (M) ....................................................................................... 146
5.6.4 Guarded (G) ......................................................................................................................... 146
5.6.5 Endian (E) ............................................................................................................................ 146
5.6.6 User-Definable (U0–U3) ...................................................................................................... 147
5.6.7 Supported Storage Attribute Combinations ......................................................................... 147
5.7 Storage Control Registers ............................................................................................................. 147
5.7.1 Memory Management Unit Control Register (MMUCR) ...................................................... 148
5.7.2 Process ID (PID) .................................................................................................................. 151
5.8 Shadow TLB Arrays ...................................................................................................................... 151
5.9 TLB Management Instructions ...................................................................................................... 152
5.9.1 TLB Search Instruction (tlbsx[.]) .......................................................................................... 153
5.9.2 TLB Read/Write Instructions (tlbre/tlbwe) ............................................................................ 153
5.9.3 TLB Sync Instruction (tlbsync) ............................................................................................. 154
5.10 Page Reference and Change Status Management ..................................................................... 154
5.11 TLB Parity Operations ................................................................................................................. 155
5.11.1 Reading TLB Parity Bits with tlbre ..................................................................................... 155
5.11.2 Simulating TLB Parity Errors for Software Testing ............................................................ 156
6. Interrupts and Exceptions ..................................................................................... 159
6.1 Overview ....................................................................................................................................... 159
6.2 Interrupt Classes ........................................................................................................................... 159
6.2.1 Asynchronous Interrupts ...................................................................................................... 159
6.2.2 Synchronous Interrupts ........................................................................................................ 159
6.2.2.1 Synchronous, Precise Interrupts .................................................................................. 160
6.2.2.2 Synchronous, Imprecise Interrupts ............................................................................... 160
6.2.3 Critical and Non-Critical Interrupts ....................................................................................... 161
6.2.4 Machine Check Interrupts .................................................................................................... 161
6.3 Interrupt Processing ...................................................................................................................... 162
6.3.1 Partially Executed Instructions ............................................................................................. 164
6.4 Interrupt Processing Registers ...................................................................................................... 165
6.4.1 Machine State Register (MSR) ............................................................................................ 165
6.4.2 Save/Restore Register 0 (SRR0) ......................................................................................... 167
6.4.3 Save/Restore Register 1 (SRR1) ......................................................................................... 167