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User’s Manual
PPC440x5 CPU Core Preliminary
Page 64 of 589
prgmodel.fm.
September 12, 2002
2.5 Branch Processing
The four branch instructions provided by PPC440x5 are summarized in Table 2.4.2 on Page 60. In addition,
each of these instructions is described in detail in Instruction Set on page 249. The following sections provide
additional information on branch addressing, instruction fields, prediction, and registers.
2.5.1 Branch Addressing
The branch instruction (
b[l][a]) specifies the displacement of the branch target address as a 26-bit value (the
24-bit LI field right-extended with 0b00). This displacement is regarded as a signed 26-bit number covering
an address range of ±32MB. Similarly, the branch conditional instruction (bc[l][a]) specifies the displacement
as a 16-bit value (the 14-bit BD field right-extended with 0b00). This displacement covers an address range of
±32KB.
For the relative form of the branch and branch conditional instructions (b[l] and bc[l], with instruction field
AA = 0), the target address is the address of the branch instruction itself (the Current Instruction Address, or
CIA) plus the signed displacement. This address calculation is defined to “wrap around” from the maximum
effective address (0xFFFFFFFF) to 0x0000 0000, and vice-versa.
For the absolute form of the branch and branch conditional instructions (ba[l] and bca[l], with instruction field
AA = 1), the target address is the sign-extended displacement. This means that with absolute forms of the
branch and branch conditional instructions, the branch target can be within the first or last 32MB or 32KB of
the address space, respectively.
The other two branch instructions, bclr (branch conditional to LR) and bcctr (branch conditional to CTR), do
not use absolute nor relative addressing. Instead, they use indirect addressing, in which the target of the
branch is specified indirectly as the contents of the LR or CTR.
2.5.2 Branch Instruction BI Field
Conditional branch instructions can optionally test one bit of the CR, as indicated by instruction field BO[0]
(see BO field description below). The value of instruction field BI specifies the CR bit to be tested (0-31). The
BI field is ignored if BO[0] = 1. The branch (b[l][a]) instruction is by definition unconditional, and hence does
not have a BI instruction field. Instead, the position of this field is part of the LI displacement field.
2.5.3 Branch Instruction BO Field
The BO field specifies the condition under which a conditional branch is taken, and whether the branch decre-
ments the CTR. The branch (b[l][a]) instruction is by definition unconditional, and hence does not have a BO
instruction field. Instead, the position of this field is part of the LI displacement field.
Conditional branch instructions can optionally test one bit in the CR. This option is selected when BO[0] = 0; if
BO[0] = 1, the CR does not participate in the branch condition test. If the CR condition option is selected, the
condition is satisfied (branch can occur) if the CR bit selected by the BI instruction field matches BO[1].
Conditional branch instructions can also optionally decrement the CTR by one, and test whether the decre-
mented value is 0. This option is selected when BO[2] = 0; if BO[2] = 1, the CTR is not decremented and
does not participate in the branch condition test. If CTR decrement option is selected, BO[3] specifies the
condition that must be satisfied to allow the branch to be taken. If BO[3] = 0, CTR ≠ 0 is required for the
branch to occur. If BO[3] = 1, CTR = 0 is required for the branch to occur.