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User’s Manual
Preliminary PPC440x5 CPU Core
prgmodel.fm.
September 12, 2002
Page 39 of 589
2. Programming Model
The programming model of the PPC440x5 core describes how the following features and operations of the
core appear to programmers:
• Storage addressing (including data types and byte ordering), starting on page 39
• Registers, starting on page 47
• Instruction classes, starting on page 53
• Instruction set, starting on page 56
• Branch processing, starting on page 64
• Integer processing, starting on page 71
• Processor control, starting on page 74
• User and supervisor state, starting on page 80
• Speculative access, starting on page 81
• Synchronization, starting on page 82
2.1 Storage Addressing
As a 32-bit implementation of the Book-E Enhanced PowerPC Architecture, the PPC440x5 core implements
a uniform 32-bit effective address (EA) space. Effective addresses are expanded into virtual addresses and
then translated to 36-bit (64GB) real addresses by the memory management unit (see Memory Management
on page 133 for more information on the translation process). The organization of the real address space into
a physical address space is system-dependent, and is described in the user’s manuals for chip-level products
that incorporate a PPC440x5 core.
The PPC440x5 generates an effective address whenever it executes a storage access, branch, cache
management, or translation lookaside buffer (TLB) management instruction, or when it fetches the next
sequential instruction.
2.1.1 Storage Operands
Bytes in storage are numbered consecutively starting with 0. Each number is the address of the corre-
sponding byte.
Data storage operands accessed by the integer load/store instructions may be bytes, halfwords, words, or—
for load/store multiple and string instructions—a sequence of words or bytes, respectively. Data storage oper-
ands accessed by auxiliary processor (AP) load/store instructions can be bytes, halfwords, words, double-
words, or quadwords. The address of a storage operand is the address of its first byte (that is, of its lowest-
numbered byte). Byte ordering can be either big endian or little endian, as controlled by the endian storage
attribute (see Byte Ordering on page 42; also see Endian (E) on page 146 for more information on the endian
storage attribute).
Operand length is implicit for each scalar storage access instruction type (that is, each storage access
instruction type other than the load/store multiple and string instructions). The operand of such a scalar
storage access instruction has a “natural” alignment boundary equal to the operand length. In other words,
the ‘natural’ address of an operand is an integral multiple of the operand length. A storage operand is said to
be aligned if it is aligned at its natural boundary: otherwise it is said to be unaligned.