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User’s Manual
Preliminary PPC440x5 CPU Core
prgmodel.fm.
September 12, 2002
Page 75 of 589
• Processor Version Register (PVR)
Indicates the specific implementation of a processor
• Processor Identification Register (PIR)
Indicates the specific instance of a processor in a multi-processor system
• Core Configuration Register 0 (CCR0)
Controls specific processor functions, such as instruction prefetch
• Reset Configuration (RSTCFG)
Reports the values of certain fields of the TLB as supplied at reset
Except for the MSR, each of these registers is described in more detail in the following sections. The MSR is
described in more detail in Interrupts and Exceptions on page 159.
2.7.1 Special Purpose Registers General (USPRG0, SPRG0–SPRG7)
USPRG0 and SPRG0–SPRG7 are provided for general purpose, system-dependent software use. One
common system usage of these registers is as temporary storage locations. For example, a routine might
save the contents of a GPR to an SPRG, and later restore the GPR from it. This is faster than a save/restore
to a memory location. These registers are written using mtspr and read using mfspr.
Access to USPRG0 is non-privileged for both read and write.
Access to SPRG4–SPRG7 is non-privileged for read but privileged for write, and hence different SPR
numbers are used for reading than for writing.
Access to SPRG0–SPRG3 is privileged for both read and write.
2.7.2 Processor Version Register (PVR)
The PVR is a read-only register typically used to identify a specific processor core and chip implementation.
Software can read the PVR to determine processor core and chip hardware features. The PVR can be read
into a GPR using mfspr.
Refer to PowerPC 440x5 Embedded Processor Data Sheet for the PVR value.
Access to the PVR is privileged.
Figure 2-8. Special Purpose Registers General (USPRG0, SPRG0–SPRG7)
0:31 General data Software value; no hardware usage.
0 31