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User’s Manual
PPC440x5 CPU Core Preliminary
Page 226 of 589
debug.fm.
September 12, 2002
interrupt has occurred imprecisely. On the other hand, if the IAC mode is set to either range inclusive or range
exclusive mode, then IAC debug events cannot occur when operating in internal debug mode with
MSR[DE] = 0, unless external debug mode and/or debug wait mode is also enabled.
When operating in trace mode, the occurrence of an IAC debug event simply sets the corresponding IAC field
of the DBSR and is indicated over the trace interface, and instruction execution continues.
8.3.2 Data Address Compare (DAC) Debug Event
DAC debug events occur when execution is attempted of a load, store, or cache management instruction for
which the data storage address and other parameters match the DAC conditions specified by DBCR0,
DBCR2, and the DAC registers. There are two DAC registers on the PPC440x5, DAC1 and DAC2.
Depending on the DAC mode specified by DBCR2, these DAC registers can be used to specify two indepen-
dent, exact DAC addresses, or they can be configured to operate as a pair. When operating as a pair, then
can specify either a range of data storage addresses for which DAC debug events should occur, or a combi-
nation of an address and an address bit mask for selective comparison with the data storage address.
Note that for integer load and store instructions, and for cache management instructions, the address that is
used in the DAC comparison is the starting data address calculated as part of the instruction execution. As
explained in the instruction definitions for the cache management instructions, the target operand of these
instructions is an aligned cache block, which on the PPC440x5 is 32 bytes. Therefore, the storage reference
for these instructions effectively ignores the low-order five bits of the calculated data address, and the entire
aligned 32-byte cache block—which starts at the calculated data address as modified with the low-order five
bits set to 0b00000—is accessed. However, the DAC comparison does not take into account this implicit 32-
byte alignment of the storage reference of a cache management instruction, and instead the DAC compar-
ison considers the entire data address, as calculated according to the instruction definition.
On the other hand, for auxiliary processor load and store instructions, the AP interface can specify that the
PPC440x5 should force the storage access to be aligned on an operand-size boundary, by zeroing the
appropriate number of low-order address bits. In such a case, the DAC comparison is performed against this
modified, alignment-forced address, rather than the original address as calculated according to the instruction
definition.
8.3.2.1 DAC Debug Event Fields
There are several fields in DBCR0 and DBCR2 which are used to specify the DAC conditions, as follows:
DAC Event Enable Field
DBCR0[DAC1R, DAC1W, DAC2R, DAC2W] are the individual DAC event enables for the two
DAC events DAC1 and DAC2. For each of the two DAC events, there is one enable for DAC read
events, and another for DAC write events. Load, dcbt, dcbtst, icbi, and icbt instructions may
cause DAC read events, while store, dcbst, dcbf, dcbi, and dcbz instructions may cause DAC
write events (see DAC Debug Events Applied to Various Instruction Types on page 230 for more
information on these instructions and the types of DAC debug events they may cause). For a
given DAC event to occur, the corresponding DAC event enable bit in DBCR0 for the particular
operation type must be set. When a DAC event occurs, the corresponding DBSR[DAC1R,
DAC1W, DAC2R, DAC2W] bit is set. These same DBSR bits are shared by DVC debug events
(see Data Value Compare (DVC) Debug Event on page 231).