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User’s Manual
PPC440x5 CPU Core Preliminary
Page 140 of 589
mmu.fm.
September 12, 2002
Figure 5-1 illustrates the criteria for a virtual address to match a specific TLB entry, while Table 5-2 defines
the page sizes associated with each SIZE field value, and the associated comparison of the effective address
to the EPN field.
5.4 Address Translation
Once a TLB entry is found which matches the virtual address associated with a given storage access, as
described in Page Identification on page 138, the virtual address is translated to a real address according to
the procedures described in this section.
Table 5-2. Page Size and Effective Address to EPN Comparison
SIZE Page Size EA to EPN Comparison
0b0000
0b0001
0b0010
0b0011
0b0100
0b0101
0b0110
0b0111
0b1000
0b1001
0b1010
0b1011
0b1100
0b1101
0b1110
0b1111
1KB
4KB
16KB
64KB
256KB
1MB
not supported
16MB
not supported
256MB
not supported
not supported
not supported
not supported
not supported
not supported
EPN
0:21
=? EA
0:21
EPN
0:19
=? EA
0:19
EPN
0:17
=? EA
0:17
EPN
0:15
=? EA
0:15
EPN
0:13
=? EA
0:13
EPN
0:11
=? EA
0:11
not supported
EPN
0:7
=? EA
0:7
not supported
EPN
0:3
=? EA
0:3
not supported
not supported
not supported
not supported
not supported
not supported
TLB entry matches virtual address
MSR[IS] for instruction fetches, or
MSR[DS] for data storage accesses, or
MMUCR[STS] for tlbsx[.]
AS
Legend:
EA effective address
31 – log
2
(page size)
N-1
{
=0?
private page
shared page
=?
=?
PID register for storage accesses
Process ID
TLBentry[V]
TLBentry[TS]
AS
Process ID
TLBentry[TID]
TLBentry[EPN]
0:N-1
EA
0:N-1
{
=?
MMUCR[STID] for tlbsx[.]
F
igure 5-1. Virtual Address to TLB Entry Match Process