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User’s Manual
Preliminary PPC440x5 CPU Core
intrupts.fm.
September 12, 2002
Page 177 of 589
Table Notes
1. Although it is not specified as part of Book E, it is common for system implementations to provide, as part of the
interrupt controller, independent mask and status bits for the various sources of Critical Input and External Input
interrupts.
2. Machine Check interrupts are not classified as asynchronous nor synchronous. They are also not classified as
critical or non-critical, because they use their own unique set ot Save/Restore Registers, MCSRR0/1. See
Machine Check Interrupts on page 161, and Machine Check Interrupt on page 178.
3. Debug exceptions have special rules regarding their interrupt classification (synchronous or asynchronous,
and precise or imprecise), depending on the particular debug mode being used and other conditions (see
Debug Interrupt on page 195).
4. In general, when an interrupt causes a particular ESR bit or bits to be set as indicated in the table, it also
causes all other ESR bits to be cleared. Special rules apply to the ESR[MCI] field; see Machine Check
Interrupt on page 178. If no ESR setting is indicated for any of the exception types within a given interrupt type,
then the ESR is unchanged for that interrupt type.
The syntax for the ESR setting indication is as follows:
[xxx] means ESR[xxx] may be set
[xxx,yyy,zzz] means any one (or none) of ESR[xxx] or ESR[yyy] or ESR[zzz] may be set, but never more than one
{xxx,yyy,zzz} means that any combination of ESR[xxx], ESR[yyy], and ESR[zzz] may be set, including all or none
xxx means ESR[xxx] will be set
5. Byte Ordering exception type Data Storage interrupts can only occur when the PPC440x5 core is connected to
a floating-point unit or auxiliary processor, and then only when executing FP or AP load or store instructions.
See Data Storage Interrupt on page 181 for more detailed information on these kinds of exceptions.
6. Byte Ordering exception type Instruction Storage interrupts are defined by the PowerPC Book-E architecture,
but cannot occur within the PPC440x5 core. The core is capable of executing instructions from both big endian
and little endian code pages.
7. Unimplemented Operation exception type Program interrupts can only occur when the PPC440x5 core is
connected to a floating-point unit or auxiliary processor, and then only when executing instruction opcodes
which are recognized by the floating-point unit or auxiliary processor but are not implemented within the
hardware.
8. Floating-Point Unavailable and Auxiliary Processor Unavailable interrupts, as well as Floating-Point Enabled
and Auxiliary Processor Enabled exception type Program interrupts, can only occur when the PPC440x5 core
is connected to a floating-point unit or auxiliary processor, and then only when executing instruction opcodes
which are recognized by the floating-point unit or auxiliary processor, respectively.
Table 6-2. Interrupt and Exception Types
IVOR Interrupt Type Exception Type
Asynchronous
Synchronous, Precise
Synchronous, Imprecise
Critical
ESR
(See Note 4)
MSR Mask Bit(s)
DBCR0/TCR Mask Bit
Notes