IBM PPC440X5 Computer Hardware User Manual


 
bcctr
Branch Conditional to Count Register
Preliminary PPC440x5 CPU Core User’s Manual
instrset.fm.
September 12, 2002 Page 275 of 589
bcctr
Branch Conditional to Count Register
if (BO
0
=1 (CR
BI
=BO
1
)) then
NIA
CTR
0:29
||
2
0
else
NIA
CIA + 4
if LK = 1 then
(LR)
CIA + 4
PC
NIA
If BO
0
contains 0, then the CR bit specified by the BI field is compared to BO
1
as part of the branch condition.
If BO
0
contains 1, then the CR is not tested as part of the branch condition, and the BI field is ignored.
The next instruction address (NIA) is either the effective address of the branch target, or the address of the
instruction after the branch, depending on whether the branch is taken or not. The branch target address is
formed by concatenating two 0-bits to the right of the 30 most significant bits of the CTR.
BO
4
affects branch prediction, a performance-improvement feature. See Branch Prediction on page 65 for a
complete discussion.
Instruction execution resumes with the instruction at the NIA.
If the LK field contains 1, then (CIA + 4) is placed into the LR.
Registers Altered
LR if LK contains 1
Invalid Instruction Forms
Reserved fields
•IfBO
2
contains 0, the instruction form is invalid, and the result of the instruction (in particular, the branch
target address and whether or not the branch is taken) is undefined. The architecture does not permit the
combination of decrementing the CTR as part of the branch condition, together with using the CTR as the
branch target address.
bcctr BO, BI LK =0
bcctrl BO, BI LK =1
19 BO BI 528 LK
0 6 11 16 21 31
Table 9-9. Extended Mnemonics for bcctr, bcctrl
Mnemonic Operands Function
Other Registers
Altered
bctr
Branch unconditionally to address in CTR.
Extended mnemonic for
bcctr 20,0
bctrl
Extended mnemonic for
bcctrl 20,0
(LR) CIA + 4.