Filter
Top Products
User’s Manual
PPC440x5 CPU Core Preliminary
Page 8 of 583
ppc440x5TOC.fm.
September 12, 2002
7.4 Watchdog Timer ............................................................................................................................ 213
7.5 Timer Control Register (TCR) ....................................................................................................... 215
7.6 Timer Status Register (TSR) ......................................................................................................... 216
7.7 Freezing the Timer Facilities ......................................................................................................... 217
7.8 Selection of the Timer Clock Source ............................................................................................. 217
8. Debug Facilities ...................................................................................................... 219
8.1 Support for Development Tools ..................................................................................................... 219
8.2 Debug Modes ................................................................................................................................ 219
8.2.1 Internal Debug Mode ........................................................................................................... 219
8.2.2 External Debug Mode .......................................................................................................... 220
8.2.3 Debug Wait Mode ................................................................................................................ 220
8.2.4 Trace Debug Mode .............................................................................................................. 221
8.3 Debug Events ................................................................................................................................ 221
8.3.1 Instruction Address Compare (IAC) Debug Event ............................................................... 222
8.3.1.1 IAC Debug Event Fields ............................................................................................... 222
8.3.1.2 IAC Debug Event Processing ....................................................................................... 225
8.3.2 Data Address Compare (DAC) Debug Event ....................................................................... 226
8.3.2.1 DAC Debug Event Fields .............................................................................................. 226
8.3.2.2 DAC Debug Event Processing ..................................................................................... 229
8.3.2.3 DAC Debug Events Applied to Instructions that Result in Multiple Storage Accesses . 230
8.3.2.4 DAC Debug Events Applied to Various Instruction Types ........................................... 230
8.3.3 Data Value Compare (DVC) Debug Event ........................................................................... 231
8.3.3.1 DVC Debug Event Fields .............................................................................................. 232
8.3.3.2 DVC Debug Event Processing ..................................................................................... 233
8.3.3.3 DVC Debug Events Applied to Instructions that Result in Multiple Storage Accesses . 233
8.3.3.4 DVC Debug Events Applied to Various Instruction Types ........................................... 233
8.3.4 Branch Taken (BRT) Debug Event ...................................................................................... 234
8.3.5 Trap (TRAP) Debug Event ................................................................................................... 234
8.3.6 Return (RET) Debug Event .................................................................................................. 235
8.3.7 Instruction Complete (ICMP) Debug Event .......................................................................... 235
8.3.8 Interrupt (IRPT) Debug Event .............................................................................................. 236
8.3.9 Unconditional Debug Event (UDE) ...................................................................................... 237
8.3.10 Debug Event Summary ...................................................................................................... 237
8.4 Debug Reset ................................................................................................................................. 238
8.5 Debug Timer Freeze ..................................................................................................................... 238
8.6 Debug Registers ............................................................................................................................ 238
8.6.1 Debug Control Register 0 (DBCR0) ..................................................................................... 239
8.6.2 Debug Control Register 1 (DBCR1) ..................................................................................... 240
8.6.3 Debug Control Register 2 (DBCR2) ..................................................................................... 243
8.6.4 Debug Status Register (DBSR) .......................................................................................... 244
8.6.5 Instruction Address Compare Registers (IAC1–IAC4) ......................................................... 245
8.6.6 Data Address Compare Registers (DAC1–DAC2) ............................................................... 246
8.6.7 Data Value Compare Registers (DVC1–DVC2) ................................................................... 246
8.6.8 Debug Data Register (DBDR) .............................................................................................. 247
9. Instruction Set ........................................................................................................ 249
9.1 Instruction Set Portability ............................................................................................................... 250
9.2 Instruction Formats ........................................................................................................................ 250