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User’s Manual
Preliminary PPC440x5 CPU Core
debug.fm.
September 12, 2002
Page 227 of 589
DAC Mode Field
DBCR2[DAC12M] controls the comparison mode for the DAC1 and DAC2 events. There are four
comparison modes supported by the PPC440x5:
• Exact comparison mode (DBCR2[DAC12M] = 0b00)
In this mode, the data address is compared to the value in the corresponding DAC register, and the
DAC event occurs only if the comparison is an exact match.
• Address bit mask mode (DBCR2[DAC12M] = 0b01)
In this mode, the DAC1 or DAC2 event occurs only if the data address matches the value in the
DAC1 register, as masked by the value in the DAC2 register. That is, the DAC1 register specifies an
address value, and the DAC2 register specifies an address bit mask which determines which bit of
the data address should participate in the comparison to the DAC1 value. For every bit set to 1 in the
DAC2 register, the corresponding data address bit must match the value of the same bit position in
the DAC1 register. For every bit set to 0 in the DAC2 register, the corresponding address bit compar-
ison does not affect the result of the DAC event determination.
This comparison mode is useful for detecting accesses to a particular byte address, when the
accesses may be of various sizes. For example, if the debugger is interested in detecting accesses to
byte address 0x00000003, then these accesses may occur due to a byte access to that specific
address, or due to a halfword access to address 0x00000002, or due to a word access to address
0x00000000. By using address bit mask mode and specifying that the low-order two bits of the
address should be ignored (that is, setting the address bit mask in DAC2 to 0xFFFFFFFC), the
debugger can detect each of these types of access to byte address 0x00000003.
When the data address matches the address bit mask mode conditions, either one or both of the
DAC debug event bits corresponding to the operation type (read or write) will be set in the DBSR, as
determined by which of the corresponding two DAC event enable bits are set in DBCR0. That is,
when an address bit mask mode DAC debug event occurs, the setting of DBCR2[DAC1R, DAC1W,
DAC2R, DAC2W] will determine whether one or the other or both of the DBSR[DAC1R, DAC1W,
DAC2R, DAC2W] bits corresponding to the operation type are set. It is a programming error to set
the DAC mode field to address bit mask mode without also enabling at least one of the four DAC
event enable bits in DBCR0.
• Range inclusive comparison mode (DBCR2[DAC12M] = 0b10)
In this mode, the DAC1 or DAC2 event occurs only if the data address is within the range defined by
the DAC1 and DAC2 register values, as follows: DAC1 ≤ address < DAC2.
When the data address falls within the specified range, either one or both of the DAC debug event
bits corresponding to the operation type (read or write) will be set in the DBSR, as determined by
which of the corresponding two DAC event enable bits are set in DBCR0. That is, when a range inclu-
sive mode DAC debug event occurs, the setting of DBCR2[DAC1R, DAC1W, DAC2R, DAC2W] will
determine whether one or the other or both of the DBSR[DAC1R, DAC1W, DAC2R, DAC2W] bits
corresponding to the operation type are set. It is a programming error to set the DAC mode field to a
range comparison mode (either inclusive or exclusive) without also enabling at least one of the four
DAC event enable bits in DBCR0.
• Range exclusive comparison mode (DBCR2[DAC12M] = 0b11)
In this mode, the DAC1 or DAC2 event occurs only if the data address is outside the range defined by
the DAC1 and DAC2 register values, as follows: address < DAC1 or address ≥ DAC2.