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User’s Manual
Preliminary PPC440x5 CPU Core
init.fm.
September 12, 2002
Page 93 of 589
1. Set MSR[CE] to enable/disable Critical Input and Watchdog Timer interrupts
2. Set MSR[EE] to enable/disable External Input, Decrementer, and Fixed Interval Timer interrupts
3. Set MSR[DE] to enable/disable Debug interrupts
4. Set MSR[ME] to enable/disable Machine Check interrupts
Software should first check the status of the ESR[MCI] field and MCSR[MCS] field to determine
whether any Machine Check exceptions have occurred after these fields were cleared by reset and
before Machine Check interrupts were enabled (by this step). Any such exceptions would have set
ESR[MCI] or MCSR[MCS] to 1, and this status can only be cleared explicitly by software. After the
MCSR[MCS] field is known to be clear, the MCSR status bits (MCSR[1:8]) should be cleared by soft-
ware to avoid possible confusion upon later service of a machine check interrupt. Once MSR[ME]
has been set to 1, subsequent Machine Check exceptions will result in a Machine Check interrupt.
5. Context synchronize to establish new MSR context (isync)
16. Initialize any other processor core resources as required by the system (GPRs, SPRGs, and so on)
17. Initialize any other facilities outside the processor core as required by the system
18. Initialize system memory as required by the system software
Synchronize any program memory changes as required. (See Self-Modifying Code on page 106 for more
information on the instruction sequence necessary to synchronize changes to program memory prior to
executing the new instructions)
19. Start the system software
System software is generally responsible for initializing and/or managing the rest of the MSR fields,
including:
1. MSR[FP] to enable or disable the execution of floating-point instructions
2. MSR[FE0,FE1] to enable/disable Floating-Point Enabled exception type Program interrupts
3. MSR[PR] to specify user mode or supervisor mode
4. MSR[IS,DS] to specify application address space or system address space for instructions and data
5. MSR[WE] to place the processor into Wait State (halt execution pending an interrupt)