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mbar
Memory Barrier
Preliminary PPC440x5 CPU Core User’s Manual
instrset.fm.
September 12, 2002 Page 357 of 589
mbar
Memory Barrier
The mbar instruction ensures that all loads and stores preceding mbar complete with respect to main
storage before any loads and stores following mbar access main storage.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
• None
Invalid Instruction Forms
• Reserved fields
Programming Note
Architecturally, mbar merely orders storage accesses, and does not perform execution nor context synchro-
nization (see Synchronization on page 82). Therefore, non-storage access instructions after mbar could
complete before the storage access instructions which were executed prior to mbar have actually completed
their storage accesses. The msync instruction, on the other hand, is execution synchronizing, and does
guarantee that all storage accesses initiated by instructions executed prior to the msync have completed
before any instructions after the msync begin execution. However, the PPC440x5 core implements the mbar
instruction identically to the msync instruction, and thus both are execution synchronizing.
Software should nevertheless use the correct instruction (mbar or msync) as called for by the specific
ordering and synchronizing requirements of the application, in order to guarantee portability to other imple-
mentations.
See Storage Ordering and Synchronization on page 84 for additional information on the use of the msync
and mbar instructions.
Architecture Note
mbar replaces the PowerPC eieio instruction. mbar uses the same opcode as eieio; PowerPC applications
which used eieio will get the function of mbar when executed on a PowerPC Book-E implementation. mbar
is architecturally “stronger” than eieio, in that eieio forced separate ordering amongst different categories of
storage accesses, while mbar forces such ordering amongst all storage accesses as a single category.
mbar
31 854
0 6 21 31