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User’s Manual
Preliminary PPC440x5 CPU Core
mmu.fm.
September 12, 2002
Page 133 of 589
5. Memory Management
The PPC440x5 supports a uniform, 4 gigabyte (GB) effective address (EA) space, and a 64GB (36-bit) real
address (RA) space. The PPC440x5 memory management unit (MMU) performs address translation
between effective and real addresses, as well as protection functions. With appropriate system software, the
MMU supports:
• Translation of effective addresses into real addresses
• Software control of the page replacement strategy
• Page-level access control for instruction and data accesses
• Page-level storage attribute control
5.1 MMU Overview
The PPC440x5 generates effective addresses for instruction fetches and data accesses. An effective
address is a 32-bit address formed by adding an index or displacement to a base address (see Effective
Address Calculation on page 41). Instruction effective addresses are for sequential instruction fetches, and
for fetches caused by changes in program flow (branches and interrupts). Data effective addresses are for
load, store and cache management instructions. The MMU expands effective addresses into virtual
addresses (VAs) and then translates them into real addresses (RAs); the instruction and data caches use
real addresses to access memory.
The PPC440x5 MMU supports demand-paged virtual memory and other management schemes that depend
on precise control of effective to real address mapping and flexible memory protection. Translation misses
and protection faults cause precise interrupts. The hardware provides sufficient information to correct the
fault and restart the faulting instruction.
The MMU divides storage into pages. The page represents the granularity of address translation, access
control, and storage attribute control. PowerPC Book-E architecture defines sixteen page sizes, of which the
PPC440x5 MMU supports eight. These eight page sizes (1KB, 4KB, 16KB, 64KB, 256KB, 1MB, 16MB, and
256MB) are simultaneously supported. A valid entry for a page referenced by an effective address must be in
the translation lookaside buffer (TLB) in order for the address to be accessed. An attempt to access an
address for which no TLB entry exists causes an Instruction or Data TLB Error interrupt, depending on the
type of access (instruction or data). See Interrupts and Exceptions on page 159 for more information on these
and other interrupt types.
The TLB is parity protected against soft errors. If such errors are detected, the CPU can be configured to
vector to the machine check interrupt handler, where software can take appropriate action. The details of
parity checking and suggested interrupt handling are described below.
5.1.1 Support for PowerPC Book-E MMU Architecture
The Book-E Enhanced PowerPC Architecture defines specific requirements for MMU implementations, but
also leaves the details of several features implementation-dependent. The PPC440x5 core is fully compliant
with the required MMU mechanisms defined by PowerPC Book-E, but a few optional mechanisms are not
supported. These are: