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lwarx
Load Word and Reserve Indexed
Preliminary PPC440x5 CPU Core User’s Manual
instrset.fm.
September 12, 2002 Page 339 of 589
lwarx
Load Word and Reserve Indexed
EA ← (RA|0) + (RB)
RESERVE
← 1
(RT)
← MS(EA,4)
An effective address (EA) is formed by adding an index to a base address. The index is the contents of
register RB. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise.
The word at the EA is placed into register RT.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Execution of the lwarx instruction sets the reservation bit.
Registers Altered
•RT
Invalid Instruction Forms
• Reserved fields
Programming Note
The lwarx and stwcx. instructions are typically paired in a loop, as shown in the following example, to create
the effect of an atomic operation to a memory area used as a semaphore between multiple processes. Only
lwarx can set the reservation bit to 1. stwcx. sets the reservation bit to 0 upon its completion, whether or not
stwcx. actually stored (RS) to memory. CR[CR0]
2
must be examined to determine whether (RS) was sent to
memory.
loop: lwarx # read the semaphore from memory; set reservation
“alter” # change the semaphore bits in the register as required
stwcx. # attempt to store the semaphore; reset reservation
bne loop # some other process intervened and cleared the reservation prior to the above
# stwcx.; try again
The PowerPC Book-E architecture specifies that the EA for the lwarx instruction must be word-aligned (that
is, a multiple of 4 bytes); otherwise, the result is undefined. Although the PPC440x5 will execute lwarx
regardless of the EA alignment, in order for the operation of the pairing of lwarx and stwcx. to produce the
desired result, software must ensure that the EA for both instructions is word-aligned. This requirement is due
to the manner in which misaligned storage accesses may be broken up into separate, aligned accesses by
the PPC440x5.
lwarx RT, RA, RB
31 RT RA RB 20
0 6 11 16 21 31