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User’s Manual
PPC440x5 CPU Core Preliminary
Page 108 of 589
cache.fm.
September 12, 2002
Alternatively, software can execute an iccci instruction, which flash invalidates the entire instruction cache
without regard to the addresses with which the cache lines are associated.
4.2.4 Instruction Cache Control and Debug
The PPC440x5 core provides various registers and instructions to control instruction cache operation and to
help debug instruction cache problems.
4.2.4.1 Instruction Cache Management and Debug Instruction Summary
For detailed descriptions of the instructions summarized in this section, see Instruction Set on page 249 Also,
see Instruction Cache Coherency on page 106 for more information on how these instructions are used to
manage coherency in the instruction cache.
In the instruction descriptions, the term “block” describes the unit of storage operated on by the cache block
instructions. For the PPC440x5 core, this is the same as a cache line.
The following instructions are used by software to manage the instruction cache:
4.2.4.2 Core Configuration Register 0 (CCR0)
The CCR0 register controls the speculative prefetch mechanism and the behavior of the icbt instruction. The
CCR0 register also controls various other functions within the PPC440x5 core that are unrelated to the
instruction cache. Each of the these functions is discussed in more detail in the related sections of this
manual.
Figure 4-5 illustrates the fields of the CCR0 register.
icbi Instruction Cache Block Invalidate
Invalidates a cache block.
icbt Instruction Cache Block Touch
Initiates a block fill, enabling a program to begin a cache block fetch before the program
needs an instruction in the block. The program can subsequently branch to the
instruction address and fetch the instruction without incurring a cache miss.
See icbt Operation on page 111.
iccci Instruction Cache Congruence Class Invalidate
Flash invalidates the entire instruction cache. Execution of this instruction is privileged.
icread Instruction Cache Read
Reads a cache line (tag and data) from a specified index of the instruction cache, into a
set of SPRs. Execution of this instruction is privileged.
See icread Operation on page 112.