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User’s Manual
Preliminary PPC440x5 CPU Core
prgmodel.fm.
September 12, 2002
Page 77 of 589
Figure 2-11. Core Configuration Register 0 (CCR0)
0 Reserved
1 PRE
Parity Recoverability Enable
0 Semi-recoverable parity mode enabled
for data cache
1 Fully recoverable parity mode enabled
for data cache
Must be set to 1 to guarantee full recoverability
from MMU and data cache parity errors.
2:3 Reserved
4 CRPE
Cache Read Parity Enable
0 Disable parity information reads
1 Enable parity information reads
When enabled, execution of icread, dcread, or
tlbre loads parity information into the ICDBTRH,
DCDBTRL, or target GPR, respectively.
5:9 Reserved
10 DSTG
Disable Store Gathering
0 Enabled; stores to contiguous addresses
may be gathered into a single transfer
1 Disabled; all stores to memory will be
performed independently
See Store Gathering on page 119.
11 DAPUIB
Disable APU Instruction Broadcast
0 Enabled.
1 Disabled; instructions not broadcast to
APU for decoding
This mechanism is provided as a means of reduc-
ing power consumption when an auxilliary pro-
cessor is not attached and/or is not being used.
See Initialization on page 85.
12:15
Reserved
16 DTB
Disable Trace Broadcast
0 Enabled.
1 Disabled; no trace information is
broadcast.
This mechanism is provided as a means of reduc-
ing power consumption when instruction tracing is
not needed.
See Initialization on page 85.
17 GICBT
Guaranteed Instruction Cache Block Touch
0 icbt may be abandoned without having
filled cache line if instruction pipeline
stalls.
1 icbt is guaranteed to fill cache line even
if instruction pipeline stalls.
See icbt Operation on page 111.
18 GDCBT
Guaranteed Data Cache Block Touch
0 dcbt/dcbtst may be abandoned without
having filled cache line if load/store
pipeline stalls.
1 dcbt/dcbtst are guaranteed to fill cache
line even if load/store pipeline stalls.
See Data Cache Control and Debug on
page 125.
19:22
Reserved
012 345 9101112 15 16 17 18 19 22 23 24 27 28 29 30 31
FLSTAGICBT
DTB GDCBT
ICSLC
ICSLT
DSTG
DAPUIB
PRE
CRPE