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icbt
Instruction Cache Block Touch
Preliminary PPC440x5 CPU Core User’s Manual
instrset.fm.
September 12, 2002 Page 315 of 589
This instruction is considered a “load” with respect to Data Storage exceptions. See Data Storage Interrupt on
page 181 for more information.
This instruction is considered a “load” with respect to data address compare (DAC) Debug exceptions. See
Debug Interrupt on page 195 for more information.