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User’s Manual
PPC440x5 CPU Core Preliminary
Page 82 of 589
prgmodel.fm.
September 12, 2002
The architecture provides two mechanisms for protecting against errant accesses to such “non-well-behaved”
memory addresses. The first is the guarded (G) storage attribute, and protects against speculative data
accesses. The second is the execute permission mechanism, and protects against speculative instruction
fetches. Both of these mechanisms are described in Memory Management on page 133
2.10 Synchronization
The PPC440x5 supports the synchronization operations of the PowerPC Book-E architecture. There are
three kinds of synchronization defined by the architecture, each of which is described in the following
sections.
2.10.1 Context Synchronization
The context of a program is the environment in which the program executes. For example, the mode (user or
supervisor) is part of the context, as are the address translation space and storage attributes of the memory
pages being accessed by the program. Context is controlled by the contents of certain registers and other
resources, such as the MSR and the translation lookaside buffer (TLB).
Under certain circumstances, it is necessary for the hardware or software to force the synchronization of a
program’s context. Context synchronizing operations include all interrupts except Machine Check, as well as
the isync, sc, rfi, rfci, and rfmci instructions. Context synchronizing operations satisfy the following require-
ments:
1. The operation is not initiated until all instructions preceding the operation have completed to the point at
which they have reported any and all exceptions that they will cause.
2. All instructions preceding the operation must complete in the context in which they were initiated. That is,
they must not be affected by any context changes caused by the context synchronizing operation, or any
instructions after the context synchronizing operation.
3. If the operation is the sc instruction (which causes a System Call interrupt) or is itself an interrupt, then
the operation is not initiated until no higher priority interrupt is pending (see Interrupts and Exceptions on
page 159).
4. All instructions that follow the operation must be re-fetched and executed in the context that is established
by the completion of the context synchronizing operation and all of the instructions which preceded it.
Note that context synchronizing operations do not force the completion of storage accesses, nor do they
enforce any ordering amongst accesses before and/or after the context synchronizing operation. If such
behavior is required, then a storage synchronizing instruction must be used (see Storage Ordering and
Synchronization on page 84).
Also note that architecturally Machine Check interrupts are not context synchronizing. Therefore, an instruc-
tion that precedes a context synchronizing operation can cause a Machine Check interrupt after the context
synchronizing operation occurs and additional instructions have completed. For the PPC440x5 core, this can
only occur with Data Machine Check exceptions, and not Instruction Machine Check exceptions.
The following scenarios use pseudocode examples to illustrate the effects of context synchronization. Subse-
quent text explains how software can further guarantee “storage ordering.”
1. Consider the following self-modifying code instruction sequence:
stw XYZ Store to caching inhibited address XYZ
isync