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User’s Manual
Preliminary PPC440x5 CPU Core
debug.fm.
September 12, 2002
Page 229 of 589
8.3.2.2 DAC Debug Event Processing
The behavior of the PPC440x5 upon a DAC debug event depends on the setting of DBCR2[DAC12A]. This
field of DBCR2 controls whether DAC debug events are processed in a synchronous (DBCR2[DAC12A] = 0)
or an asynchronous (DBCR2[DAC12A] = 1) fashion.
DBCR2[DAC12A] = 0 (Synchronous Mode)
When operating in external debug mode or debug wait mode, the occurrence of a DAC debug
event is recorded in the corresponding bit of the DBSR and causes the instruction execution to be
suppressed. The processor then enters the stop state and ceases the processing of instructions.
The program counter will contain the address of the instruction which caused the DAC debug
event. Similarly, when operating in internal debug mode with Debug interrupts enabled
(MSR[DE] = 1), the occurrence of a DAC debug event is recorded in the DBSR and causes the
instruction execution to be suppressed. A Debug interrupt will occur with CSRR0 set to the
address of the instruction which caused the DAC debug event.
When operating in internal debug mode (and not also in external debug mode nor debug wait
mode) with Debug interrupts disabled (MSR[DE] = 0), then a DAC debug event will set the
corresponding DAC field of the DBSR, along with the Imprecise Debug Event (IDE) field of the
DBSR. The instruction execution is not suppressed, as no Debug interrupt will occur immediately.
Instead, instruction execution continues, and a Debug interrupt will occur if and when MSR[DE] is
set to 1, thereby enabling Debug interrupts, assuming software has not cleared the DAC debug
event status from the DBSR in the meantime. Upon such a “delayed” interrupt, the Debug
interrupt handler software may query the DBSR[IDE] field to determine that the Debug interrupt
has occurred imprecisely.
When operating in trace mode, the occurrence of a DAC debug event simply sets the
corresponding DAC field of the DBSR and is indicated over the trace interface, and instruction
execution continues. DBCR2[DAC12A] does not affect the processing of DAC debug events
when operating in trace mode.
Engineering Note: When DAC debug events are enabled in any debug mode other than
trace mode, and DBCR2[DAC12A] is set to 0 (synchronous mode), in
order for the PPC440x5 to deal with a DAC-related Debug interrupt in a
synchronous fashion, the processing of all potential DAC debug event-
causing instructions (loads, stores, and cache management instructions)
is impacted by one processor cycle. This one cycle impact occurs
whether or not the instruction is actually causing a DAC debug event.
Overall processor performance is thus significantly impacted if
synchronous mode DAC debug events are enabled. In order to maintain
normal processor performance while DAC debug events are enabled and
in the absence of any actual DAC debug events, software should set
DBCR2[DAC12A] to 1.
DBCR2[DAC12A] = 1 (Asynchronous Mode)
When operating in external debug mode or debug wait mode, the occurrence of a DAC debug
event is recorded in the corresponding bit of the DBSR and causes the processor to enter stop
state and cease processing instructions. However, the determination and processing of the DAC
debug event is not handled synchronously with respect to the instruction execution. That is, the
processor may process the DAC debug event and enter the stop state either before or after the
completion of the instruction causing the event. If the DAC debug event is processed before the
completion of the instruction causing the event, then upon entering the stop state the program