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User’s Manual
PPC440x5 CPU Core Preliminary
Page 228 of 589
debug.fm.
September 12, 2002
When the data address falls outside the specified range, either one or both of the DAC debug event
bits corresponding to the operation type (read or write) will be set in the DBSR, as determined by
which of the corresponding two DAC event enable bits are set in DBCR0. That is, when a range
exclusive mode DAC debug event occurs, the setting of DBCR2[DAC1R, DAC1W, DAC2R, DAC2W]
will determine whether one or the other or both of the DBSR[DAC1R, DAC1W, DAC2R, DAC2W] bits
corresponding to the operation type are set. It is a programming error to set the DAC mode field to a
range comparison mode (either inclusive or exclusive) without also enabling at least one of the four
DAC event enable bits in DBCR0.
DAC User/Supervisor Field
DBCR2[DAC1US, DAC2US] are the individual DAC user/supervisor fields for the two DAC
events. The DAC user/supervisor fields specify what operating mode the processor must be in
order for the corresponding DAC event to occur. The operating mode is determined by the
Problem State field of the Machine State Register (MSR[PR]; see User and Supervisor Modes on
page 80). When the DAC user/supervisor field is 0b00, the operating mode does not matter—the
DAC debug event may occur independent of the state of MSR[PR]. When this field is 0b10, the
processor must be operating in supervisor mode (MSR[PR] = 0). When this field is 0b11, the
processor must be operating in user mode (MSR[PR] = 1). The DAC user/supervisor field value of
0b01 is reserved.
If the DAC mode is set to one of the “paired” modes (address bit mask mode, or one of the two
range modes), it is a programming error (and the results of any data address comparison are
undefined) if DBCR2[DAC1US] and DBCR2[DAC2US] are not set to the same value.
DAC Effective/Real Address Field
DBCR2[DAC1ER, DAC2ER] are the individual DAC effective/real address fields for the two DAC
events. The DAC effective/real address fields specify whether the instruction address comparison
should be performed using the effective, virtual, or real address (see Memory Management on
page 133) for an explanation of these different types of addresses). When the DAC effective/real
address field is 0b00, the comparison is performed using the effective address only; the DAC
debug event may occur independent of the data address space (MSR[DS]). When this field is
0b10, the DAC debug event occurs only if the effective address matches the DAC conditions and
is in virtual address space 0 (MSR[DS] = 0). Similarly, when this field is 0b11, the DAC debug
event occurs only if the effective address matches the DAC conditions and is in virtual address
space 1 (MSR[DS] = 1). Note that in these latter two modes, in which the virtual address space of
the data is considered, it is not the entire virtual address which is considered. The Process ID,
which forms the final part of the virtual address, is not considered. Finally, the DAC effective/real
address field value of 0b01 is reserved, and corresponds to the PowerPC Book-E architected real
address comparison mode, which is not supported by the PPC440x5.
If the DAC mode is set to one of the “paired” modes (address bit mask mode, or one of the two
range modes), it is a programming error (and the results of any data address comparison are
undefined) if DBCR2[DAC1ER] and DBCR2[DAC2ER] are not set to the same value.
DVC Byte Enable Field
DBCR2[DVC1BE, DVC2BE] are the individual data value compare (DVC) byte enable fields for
the two DVC events. These fields must be disabled (by being set to 4b0000) in order for the
corresponding DAC debug event to be enabled. In other words, when any of the DVC byte enable
field bits for a given DVC event are set to 1, the corresponding DAC event is disabled, and the
various DAC field conditions are used in conjunction with the DVC field conditions to determine
whether a DVC event should occur. See Data Value Compare (DVC) Debug Event on page 231
for more information on DVC events.