Filter
Top Products
tlbsx
TLB Search Indexed
Preliminary PPC440x5 CPU Core User’s Manual
instrset.fm.
September 12, 2002 Page 437 of 589
tlbsx
TLB Search Indexed
EA ← (RA|0) + (RB)
if Rc = 1
CR[CR0]
0
← 0
CR[CR0]
1
← 0
CR[CR0]
3
← XER[SO}
if Valid TLB entry matching EA and MMUCR[STID,STS] is in the TLB then
(RT)
← Index of matching TLB Entry
if Rc = 1
CR[CR0]
2
← 1
else
(RT)
← Undefined
if Rc = 1
CR[CR0]
2
← 0
An effective address is formed by adding an index to a base address. The index is the contents of register
RB. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise.
The TLB is searched for a valid entry which translates EA and MMUCR[STID,STS]. See Memory Manage-
ment on page 133 for descriptions of the TLB fields and how they participate in the determination of a match.
If a matching entry is found, its index (0 - 63) is placed into bits 26:31 of RT, and bits 0:25 are set to 0. If no
match is found, the contents of RT are undefined.
The record bit (Rc) specifies whether the results of the search will affect CR[CR0] as shown above, such that
CR[CR0]
2
can be tested if there is a possibility that the search may fail.
Registers Altered
• CR[CR0] if Rc contains 1
Invalid Instruction Forms
• None
Programming Notes
Execution of this instruction is privileged.
The PPC440x5 core does not automatically synchronize the context of the MMUCR[STID] field between a
tlbre instruction which updates the field, and a tlbsx[.] instruction which uses it as a source operand. There-
fore, software must execute an isync instruction between the execution of a tlbre instruction and a subse-
quent tlbsx[.] instruction to ensure that the tlbsx[.] instruction will use the new value of MMUCR[STID]. On
the other hand, the PPC440x5 core does automatically synchronize the context of MMUCR[STID] between
tlbre and tlbwe, as well as between tlbre and mfspr which specifies the MMUCR as the source SPR, so no
isync is required in these cases.
tlbsx RT, RA, RB Rc=0
tlbsx. RT, RA, RB Rc=1
31 RT RA RB 914 Rc
0 6 11 16 21 31