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User’s Manual
PPC440x5 CPU Core Preliminary
Page 198 of 589
intrupts.fm.
September 12, 2002
Since the ICMP Debug exception does not suppress the execution of the instruction causing the
exception, but rather allows it to complete before causing the interrupt, the behavior of the interrupt is
different in the special case where the instruction causing the ICMP Debug exception is itself setting
MSR[DE] to 0. In this case, the interrupt will be delayed and will occur if and when MSR[DE] is again
set to 1, assuming DBSR[ICMP] is still set. If the Debug interrupt occurs in this fashion, it will be syn-
chronous and imprecise, and CSRR0 will be set to the address of the instruction after the one which
set MSR[DE] to 1 (not the one which originally caused the ICMP Debug exception and in so doing set
MSR[DE] to 0). If the instruction which set MSR[DE] to 1 was rfi, rfci, or rfmci, then CSRR0 is set to
the address to which the rfi, rfci, or rfmci was returning, and not to the address of the instruction
which was sequentially after the rfi, rfci, or rfmci.
• For IRPT Debug exceptions, set to the address of the first instruction in the interrupt handler associ-
ated with the interrupt type that caused the IRPT Debug exception. The interrupt is asynchronous.
• For UDE Debug exceptions, set to the address of the instruction that would have executed next if the
Debug interrupt had not occurred. The interrupt is asynchronous.
For all Debug exceptions that occur while Debug interrupts are disabled (MSR[DE] = 0), the Debug inter-
rupt will be delayed and will occur if and when MSR[DE] is again set to 1, assuming the Debug exception
status is still set in the DBSR. If the Debug interrupt occurs in this fashion, CSRR0 is set to the address of
the instruction after the one which set MSR[DE]. If the instruction which set MSR[DE] was rfi, rfci, or
rfmci, then CSRR0 is set to the address to which the rfi, rfci, or rfmci was returning, and not to the
address of the instruction which was sequentially after the rfi, rfci, or rfmci. The interrupt is either syn-
chronous and imprecise, or asynchronous, depending on the type of Debug exception, as follows:
• For IAC and RET Debug exceptions, the interrupt is synchronous and imprecise.
• For BRT Debug exceptions, this scenario cannot occur. BRT Debug exceptions are not recognized
when MSR[DE]=0 if operating in internal debug mode.
• For TRAP Debug exceptions, the Debug interrupt is synchronous and imprecise. However, under
these conditions (TRAP Debug exception occurring while MSR[DE] is 0), the attempted execution of
the trap instruction for which one or more of the trap conditions is met will itself lead to a Trap excep-
tion type Program interrupt. The corresponding Debug interrupt which will occur later if and when
Debug interrupts are enabled will be in addition to the Program interrupt.
• For DAC and DVC Debug exceptions, if DBCR2[DAC12A] is 0, then the interrupt is synchronous and
imprecise. If DBCR2[DAC12A] is 1, then the interrupt is asynchronous.
• For ICMP Debug exceptions, this scenario cannot occur in this fashion. ICMP Debug exceptions are
not recognized when MSR[DE]=0 if operating in internal debug mode. However, a similar scenario
can occur when MSR[DE] is 1 at the time of the ICMP Debug exception, but the instruction whose
completion is causing the exception is itself setting MSR[DE] to 0. This scenario is described above
in the subsection on the ICMP Debug exception for which MSR[DE] is 1 at the time of the exception.
In that scenario, the interrupt is synchronous and imprecise.
• For IRPT and UDE Debug exceptions, the interrupt is asynchronous.
Critical Save/Restore Register 1 (CSRR1)
Set to the contents of the MSR at the time of the interrupt.
Machine State Register (MSR)
ME Unchanged.
All other MSR bits set to 0.