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User’s Manual
Preliminary PPC440x5 CPU Core
prgmodel.fm.
September 12, 2002
Page 55 of 589
In addition to supporting the defined instructions of PowerPC Book-E, the PPC440x5 also implements a
number of instructions which use the allocated instruction opcodes, and thus are not part of the PowerPC
Book-E architecture. Table 2-21 on page 63 identifies the allocated instructions that are implemented within
the PPC440x5 core. All of these instructions are always enabled and supported, and thus they always
perform the functions defined for them within this document, and never cause Illegal Instruction, Auxiliary
Processor Unavailable, nor Unimplemented Instruction exceptions.
The PPC440x5 also supports the use of any of the allocated opcodes by an attached auxiliary processor,
except for those allocated opcodes which have been implemented within the PPC440x5 core, as mentioned
above. Also, there is one other allocated opcode (primary opcode 31, secondary opcode 262) that has been
implemented within the PPC440x5 core and is thus not available for use by an attached auxiliary processor.
This is the opcode which was used on previous PowerPC 400 Series embedded controllers for the icbt
(Instruction Cache Block Touch) instruction. The icbt instruction is now part of the defined instruction class
for PowerPC Book-E, and uses a new opcode (primary opcode 31, secondary opcode 22). The PPC440x5
implements the new defined opcode, but also continues to support the previous opcode, in order to support
legacy software written for earlier PowerPC 400 Series implementations. The icbt instruction description in
Instruction Set on page 249 only identifies the defined opcode, although Appendix A, “Instruction Summary,”
includes both the defined and the allocated opcode in the table which lists all the instructions by opcode. In
order to ensure portability between the PPC440x5 and future PowerPC Book-E implementations, software
should take care to only use the defined opcode for icbt, and avoid usage of the previous opcode which is
now in the allocated class.
2.3.3 Preserved Instruction Class
The preserved instruction class is provided to support backward compatibility with the PowerPC Architecture,
and/or earlier versions of the PowerPC Book-E architecture. This instruction class includes opcodes which
were defined for these previous architectures, but which are no longer defined for PowerPC Book-E.
Any attempt to execute a preserved instruction results in one of the following effects:
• Performs the actions described in the previous version of the architecture, if the instruction is recognized
by the implementation
• Causes an Illegal Instruction exception type Program interrupt, if the instruction is not recognized by the
implementation.
The only preserved instruction recognized and supported by the PPC440x5 is the mftb (Move From Time
Base) opcode. This instruction was used in the the PowerPC Architecture to read the Time Base Upper
(TBU) and Time Base Lower (TBL) registers. PowerPC Book-E architecture instead defines TBU and TBL as
Special Purpose Registers (SPRs), and thus the mfspr (Move From Special Purpose Register) instruction is
used to read them. In order to enable legacy time base management software to be run on the PPC440x5,
the core also supports the preserved opcode of mftb. However, the mftb instruction is not included in the
various sections of this document that describe the implemented instructions, and software should take care
to use the currently architected mechanism of mfspr to read the time base registers, in order to guarantee
portability between the PPC440x5 and future implementations of PowerPC Book-E.
On the other hand, Appendix A, “Instruction Summary,” does identify the mftb instruction as an implemented
preserved opcode in the table which lists all the instructions by opcode.