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User’s Manual
Preliminary PPC440x5 CPU Core
ppc440x5TOC.fm.
September 12, 2002
Page 3 of 583
Contents
Figures ............................................................................................................................ 15
Tables .............................................................................................................................. 19
About This Book ............................................................................................................ 23
1. Overview .................................................................................................................... 27
1.1 PPC440x5 Features ........................................................................................................................ 27
1.2 The PPC440x5 as a PowerPC Implementation .............................................................................. 29
1.3 PPC440x5 Organization .................................................................................................................. 30
1.3.1 Superscalar Instruction Unit .................................................................................................. 30
1.3.2 Execution Pipelines ............................................................................................................... 31
1.3.3 Instruction and Data Cache Controllers ................................................................................. 31
1.3.3.1 Instruction Cache Controller (ICC) ................................................................................. 31
1.3.3.2 Data Cache Controller (DCC) ......................................................................................... 32
1.3.4 Memory Management Unit (MMU) ........................................................................................ 32
1.3.5 Timers .................................................................................................................................... 34
1.3.6 Debug Facilities ..................................................................................................................... 34
1.3.6.1 Debug Modes ................................................................................................................. 34
1.3.6.2 Development Tool Support ............................................................................................. 35
1.4 Core Interfaces ................................................................................................................................ 35
1.4.1 Processor Local Bus (PLB) ................................................................................................... 36
1.4.2 Device Control Register (DCR) Interface .............................................................................. 36
1.4.3 Auxiliary Processor Unit (APU) Port ...................................................................................... 36
1.4.4 JTAG Port .............................................................................................................................. 37
2. Programming Model ................................................................................................. 39
2.1 Storage Addressing ......................................................................................................................... 39
2.1.1 Storage Operands ................................................................................................................. 39
2.1.2 Effective Address Calculation ................................................................................................ 41
2.1.2.1 Data Storage Addressing Modes ................................................................................... 41
2.1.2.2 Instruction Storage Addressing Modes .......................................................................... 41
2.1.3 Byte Ordering ........................................................................................................................ 42
2.1.3.1 Structure Mapping Examples ......................................................................................... 43
2.1.3.2 Instruction Byte Ordering ................................................................................................ 44
2.1.3.3 Data Byte Ordering ......................................................................................................... 45
2.1.3.4 Byte-Reverse Instructions .............................................................................................. 46
2.2 Registers ......................................................................................................................................... 47
2.2.1 Register Types ...................................................................................................................... 52
2.2.1.1 General Purpose Registers ............................................................................................ 52
2.2.1.2 Special Purpose Registers ............................................................................................. 52
2.2.1.3 Condition Register .......................................................................................................... 52
2.2.1.4 Machine State Register .................................................................................................. 53
2.2.1.5 Device Control Registers ................................................................................................ 53
2.3 Instruction Classes .......................................................................................................................... 53
2.3.1 Defined Instruction Class ....................................................................................................... 53