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User’s Manual
Preliminary PPC440x5 CPU Core
intrupts.fm.
September 12, 2002
Page 183 of 589
• dcbtst
For all other instructions, if a Data Storage exception occurs, then execution of the instruction causing the
exception is suppressed, a Data Storage interrupt is generated, the interrupt processing registers are
updated as indicated below (all registers not listed are unchanged), and instruction execution resumes at
address IVPR[IVP] || IVOR2[IVO] || 0b0000.
Save/Restore Register 0 (SRR0)
Set to the effective address of the instruction causing the Data Storage interrupt.
Save/Restore Register 1 (SRR1)
Set to the contents of the MSR at the time of the interrupt.
Machine State Register (MSR)
CE, ME, DE Unchanged.
All other MSR bits set to 0.
Data Exception Address Register (DEAR)
If the instruction causing the Data Storage exception does so with respect to the memory
page targeted by the initial effective address calculated by the instruction, then the DEAR is
set to this calculated effective address. On the other hand, if the Data Storage exception only
occurs due to the instruction causing the exception crossing a memory page boundary, in
that the exception is with respect to the attributes of the page accessed after crossing the
boundary, then the DEAR is set to the address of the first byte within that page.
For example, consider a misaligned load word instruction that targets effective address
0x00000FFF, and that the page containing that address is a 4KB page. The load word will
thus cross the page boundary, and access the next page starting at address 0x00001000. If
a Read Access Control exception exists within the first page (because the Read Access
Control field for that page is 0), the DEAR will be set to 0x00000FFF. On the other hand, if
the Read Access Control field of the first page is 1, but the same field is 0 for the next page,
then the Read Access Control exception exists only for the second page and the DEAR will
be set to 0x00001000. Furthermore, the load word instruction in this latter scenario will have
been partially executed (see Partially Executed Instructions on page 164).
Exception Syndrome Register (ESR)
FP Set to 1 if the instruction causing the interrupt is a floating-point load or store;
otherwise set to 0.
ST Set to 1 if the instruction causing the interrupt is a store, dcbz, or dcbi instruction;
otherwise set to 0.
DLK
0:1
Set to 0b10 if an icbi instruction caused a Cache Locking exception; set to 0b01 if a
dcbf instruction caused a Cache Locking exception; otherwise set to 0b00. Note that
a Read Access Control exception may occur in combination with a Cache Locking
exception, in which case software would need to examine the TLB entry associated
with the address reported in the DEAR to determine whether both exceptions had
occurred, or just a Cache Locking exception.