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icbi
Instruction Cache Block Invalidate
Preliminary PPC440x5 CPU Core User’s Manual
instrset.fm.
September 12, 2002 Page 313 of 589
icbi
Instruction Cache Block Invalidate
EA ← (RA|0) + (RB)
ICBI(EA)
An effective address (EA) is formed by adding an index to a base address. The index is the contents of
register RB. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise.
If the instruction block at the EA is in the instruction cache, the cache block is marked invalid.
If the instruction block at the EA is not in the instruction cache, no additional operation is performed.
The operation specified by this instruction is performed whether or not the EA is marked as cacheable.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
• None
Invalid Instruction Forms
• Reserved fields
Programming Note
Instruction cache management instructions use MSR[DS], not MSR[IS], as part of the virtual address. Also,
the instruction cache on the PPC440x5 is “virtually-tagged”, which means that the EA is converted to a virtual
address (VA), and the VA is compared against the cache tag field. See Instruction Cache Synonyms on
page 107 for more information on the ramifications of virtual tagging on software.
Exceptions
Instruction Storage interrupts and Instruction TLB Error interrupts are associated with exceptions which occur
during instruction fetching, not during instruction execution. Execution of instruction cache management
instructions may cause Data Storage or Data TLB Error exceptions.
This instruction is considered a “load” with respect to Data Storage exceptions. See Data Storage Interrupt on
page 181 for more information.
This instruction is considered a “load” with respect to data address compare (DAC) Debug exceptions. See
Debug Interrupt on page 195 for more information.
This instruction may cause a Cache Locking type of Data Storage exception. See Data Storage Interrupt on
page 181 for more information.
icbi RA, RB
31 RA RB 982
0 6 11 16 21 31