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User’s Manual
PPC440x5 CPU Core Preliminary
Page 120 of 589
cache.fm.
September 12, 2002
A given sequence of two store operations may only be gathered together if the targeted bytes are contained
within the same aligned quadword of memory, and if they are contiguous with respect to each other. Subse-
quent store operations may continue to be gathered with the previously gathered sequence, subject to the
same two rules (same aligned quadword and contiguous with the collection of previously gathered bytes). For
example, a sequence of three store word operations to addresses 4, 8, and 0 may all be gathered together,
as the first two are contiguous with each other, and the third (store word to address 0) is contiguous with the
gathered combination of the previous two.
An additional requirement for store gathering applies to stores which target caching inhibited memory pages.
Specifically, a given store to a caching inhibited page can only be gathered with previous store operations if
the bytes targeted by the given store do not overlap with any of the previously gathered bytes. In other words,
a store to a caching inhibited page must be both contiguous and non-overlapping with the previous store
operation(s) with which it is being gathered. This ensures that the multiple write operations associated with a
sequence of store instructions which each target a common caching inhibited location will each be performed
independently on that target location.
Finally, a given store operation will not be gathered with an earlier store operation if it is separated from the
earlier store operation by an msync or an mbar instruction, or if either of the two store operations reference a
memory page which is both guarded and caching inhibited, or if store gathering is disabled altogether by
CCR0[DSTG] (see Figure 4-5 on page 109).