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User’s Manual
PPC440x5 CPU Core Preliminary
Page 32 of 589
overview.fm.
September 12, 2002
The ICC supports cache line locking, at either an 8-line or 16-line granularity, depending on cache size (16-
line for 32KB, 8-line for 8KB and 16KB). In addition, the notion of a “transient” portion of the cache is
supported, in which the cache can be configured such that only a limited portion is used for instruction cache
lines from memory pages that are designated by a storage attribute from the MMU as being transient in
nature. Such memory pages would contain code which is unlikely to be reused once the processor moves on
to the next series of instruction lines, and thus performance may be improved by preventing each series of
instruction lines from overwriting all of the “regular” code in the instruction cache.
1.3.3.2 Data Cache Controller (DCC)
The DCC handles all load and store data accesses, as well as the PowerPC data cache management instruc-
tions. All misaligned accesses are handled in hardware, with those accesses that are contained within a half-
line (16 bytes) being handled as a single request. Load and store accesses which cross a 16-byte boundary
are broken into two separate accesses by the hardware.
The DCC interfaces to the APU port to provide direct load/store access to the data cache for APU load and
store operations. Such APU load and store instructions can access up to 16 bytes (one quadword) in a single
cycle.
The data cache can be operated in a store-in (copy-back) or write-through manner, according to the write-
through storage attribute specified for the memory page by the MMU. The DCC also supports both “store-
with-allocate” and “store-without-allocate” operations, such that store operations that miss in the data cache
can either “allocate” the line in the cache by reading it in and storing the new data into the cache, or alterna-
tively bypassing the cache on a miss and simply storing the data to memory. This characteristic can also be
specified on a page-by-page basis by a storage attribute in the MMU.
The DCC also supports cache line locking and “transient” data, in the same manner as the ICC (see Instruc-
tion Cache Controller (ICC) on page 31).
The DCC provides extensive load, store, and flush queues, such that up to three outstanding line fills and up
to four outstanding load misses can be pending, and the DCC can continue servicing subsequent load and
store hits in an out-of-order fashion. Store-gathering can also be performed on caching inhibited, write-
through, and “without-allocate” store operations, for up to 16 contiguous bytes. Finally, each cache line has
four separate “dirty” bits (one per doubleword), so that the amount of data flushed on cache line replacement
can be minimized.
1.3.4 Memory Management Unit (MMU)
The PPC440x5 supports a flat, 36-bit (64GB) real (physical) address space. This 36-bit real address is gener-
ated by the MMU, as part of the translation process from the 32-bit effective address, which is calculated by
the processor core as an instruction fetch or load/store address.
The MMU provides address translation, access protection, and storage attribute control for embedded appli-
cations. The MMU supports demand paged virtual memory and other management schemes that require
precise control of logical to physical address mapping and flexible memory protection. Working with appro-
priate system level software, the MMU provides the following functions:
• Translation of the 32-bit effective address space into the 36-bit real address space
• Page level read, write, and execute access control
• Storage attributes for cache policy, byte order (endianness), and speculative memory access
• Software control of page replacement strategy