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User’s Manual
Preliminary PPC440x5 CPU Core
mmu.fm.
September 12, 2002
Page 157 of 589
tlbwe Rs,Ra,2 ; write some data to the TLB with bad parity
isync ; wait for the tlbwe(s) to finish
mtspr CCR1, Rz ; Reset CCR1[MMUPEI]
isync ; wait for the CCR1 context to update
tlbre RT,RA,WS ; tlbre with bad parity causes interrupt