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User’s Manual
Preliminary PPC440x5 CPU Core
intrupts.fm.
September 12, 2002
Page 197 of 589
Programming Note: It is a programming error for software to enable internal debug mode
(by setting DBCR0[IDM] to 1) while Debug exceptions are already
present in the DBSR. Software must first clear all DBSR Debug
exception status (that is, all fields except IDE, MRR, IAC12ATS, and
IAC34ATS) before setting DBCR0[IDM] to 1.
If a stwcx. instruction causes a DAC or DVC Debug exception, but the processor does not have the reserva-
tion from a lwarx instruction, then the Debug exception is not recorded in the DBSR and a Debug interrupt
does not occur. Instead, the instruction completes and updates CR[CR0] to indicate the failure of the store
due to the lost reservation.
If a DAC exception occurs on an lswx or stswx with a length of zero, then the instruction is treated as a
no-op, the Debug exception is not recorded in the DBSR, and a Debug interrupt does not occur.
If a DAC exception occurs on an icbt, dcbt, or dcbtst instruction which is being no-op’ed due to some
other reason (either the referenced cache block is in a caching inhibited memory page, or a Data
Storage or Data TLB Miss exception occurs), then the Debug exception is not recorded in the DBSR and
a Debug interrupt does not occur. On the other hand, if the icbt, dcbt,ordcbtst instruction is not being
no-op’ed for one of these other reasons, the DAC Debug exception does occur and is handled in the
same fashion as other DAC Debug exceptions (see below).
For all other cases, when a Debug exception occurs, it is immediately presented to the interrupt handling
mechanism. A Debug interrupt will occur immediately if MSR[DE] is 1, and the interrupt processing registers
will be updated as described below. If MSR[DE] is 0, however, then the exception condition remains set in the
DBSR. If and when MSR[DE] is subsequently set to 1, and the exception condition is still present in the
DBSR, a “delayed” Debug interrupt will then occur either as a synchronous, imprecise interrupt, or as an
asynchronous interrupt, depending on the type of Debug exception.
When a Debug interrupt occurs, the interrupt processing registers are updated as indicated below (all regis-
ters not listed are unchanged) and instruction execution resumes at address IVPR[IVP] || IVOR15[IVO] ||
0b0000.
Critical Save/Restore Register 0 (CSRR0)
For Debug exceptions that occur while Debug interrupts are enabled (MSR[DE] = 1), CSRR0
is set as follows:
• For IAC, BRT, TRAP, and RET Debug exceptions, set to the address of the instruction causing the
Debug interrupt. Execution of the instruction causing the Debug exception is suppressed, and the
interrupt is synchronous and precise.
• For DAC and DVC Debug exceptions, if DBCR2[DAC12A] is 0, set to the address of the instruction
causing the Debug interrupt. Execution of the instruction causing the Debug exception is suppressed,
and the interrupt is synchronous and precise.
If DBCR2[DAC12A] is 1, however, then DAC and DVC Debug exceptions are handled asynchro-
nously, and CSRR0 is set to the address of the instruction that would have executed next had the
Debug interrupt not occurred. This could either be the address of the instruction causing the DAC or
DVC Debug exception, or the address of a subsequent instruction.
• For ICMP Debug exceptions, set to the address of the next instruction to be executed (the instruction
after the one whose completion caused the ICMP Debug exception). The interrupt is synchronous
and precise.