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User’s Manual
Preliminary PPC440x5 CPU Core
intrupts.fm.
September 12, 2002
Page 185 of 589
Machine State Register (MSR)
CE, ME, DE Unchanged.
All other MSR bits set to 0.
Exception Syndrome Register (ESR)
BO Set to 0.
MCI Unchanged.
All other defined ESR bits are set to 0.
6.5.5 External Input Interrupt
An External Input interrupt occurs when no higher priority exception exists, an External Input exception is
presented to the interrupt mechanism, and MSR[EE] = 1. An External Input exception is caused by the activa-
tion of an asynchronous input to the PPC440x5 core. Although the only mask for this interrupt type within the
core is the MSR[EE] bit, system implementations typically provide an alternative means for independently
masking the interrupt requests from the various devices which collectively may activate the core’s External
Input interrupt request input.
Note: MSR[EE] also enables the External Input and Fixed-Interval Timer interrupts.
When an External Input interrupt occurs, the interrupt processing registers are updated as indicated below
(all registers not listed are unchanged), and instruction execution resumes at address IVPR[IVP] ||
IVOR4[IVO] || 0b0000.
Save/Restore Register 0 (SRR0)
Set to the effective address of the next instruction to be executed.
Save/Restore Register 1 (SRR1)
Set to the contents of the MSR at the time of the interrupt.
Machine State Register (MSR)
CE, ME, DE Unchanged.
All other MSR bits set to 0.
Programming Note: Software is responsible for taking any action(s) that are required by
the implementation in order to clear any External Input exception
status (such that the External Input interrupt request input signal is
deasserted) before reenabling MSR[EE], in order to avoid another,
redundant External Input interrupt
.
6.5.6 Alignment Interrupt
An Alignment interrupt occurs when no higher priority exception exists and an Alignment exception is
presented to the interrupt mechanism. An Alignment exception occurs if execution of any of the following is
attempted: