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User’s Manual
PPC440x5 CPU Core Preliminary
Page 200 of 589
intrupts.fm.
September 12, 2002
This prevents any asynchronous interrupts, as well as (in the case of MSR[DE]) any Debug interrupts
(which include both synchronous and asynchronous types).
• Branching (or sequential execution) to addresses not mapped by the TLB, or mapped without execute
access permission
This prevents Instruction Storage and Instruction TLB Error interrupts.
• Load, store, or cache management instructions to addresses not mapped by the TLB or not having the
necessary access permission (read or write)
This prevents Data Storage and Data TLB Error interrupts.
• Execution of system call (sc) or trap (tw, twi) instructions
This prevents System Call and Trap exception type Program interrupts.
• Execution of any floating-point instructions
This prevents Floating-Point Unavailable interrupts. Note that this interrupt would occur upon the execu-
tion of any floating-point instruction, due to the automatic clearing of MSR[FP]. However, even if software
were to re-enable MSR[FP], floating-point instructions must still be avoided in order to prevent Program
interrupts due to the possibility of Floating-Point Enabled and/or Unimplemented Operation exceptions.
• Reenabling of MSR[PR]
This prevents Privileged Instruction exception type Program interrupts. Alternatively, software could re-
enable MSR[PR], but avoid the execution of any privileged instructions.
• Execution of any Auxiliary Processor instructions that are not implemented in the PPC440x5 core
This prevents Auxiliary Processor Unavailable interrupts, as well as Auxiliary Processor Enabled and
Unimplemented Operation exception type Program interrupts. Note that the auxiliary processor instruc-
tions that are implemented within the PPC440x5 core do not cause any of these types of exceptions, and
can therefore be executed prior to software having saved the save/restore registers’ contents.
• Execution of any illegal instructions, or any defined instructions not implemented within the PPC440x5
core (64-bit instructions, tlbiva, mfapidi)
This prevents Illegal Instruction exception type Program interrupts.
• Execution of any instruction that could cause an Alignment interrupt
This prevents Alignment interrupts. See Alignment Interrupt on page 185 for a complete list of instruc-
tions that may cause Alignment interrupts.
• In the Machine Check handler, use of the caches and TLBs until any detected parity errors have been
corrected.
This will avoid additional parity errors.
It is not necessary for hardware or software to avoid critical class interrupts from within non-critical class inter-
rupt handlers (and hence the processor does not automatically clear MSR[CE,ME,DE] upon a non-critical
interrupt), since the two classes of interrupts use different pairs of save/restore registers to save the instruc-
tion address and MSR. The converse, however, is not true. That is, hardware and software must cooperate in
the avoidance of both critical and non-critical class interrupts from within critical class interrupt handlers, even
though the two classes of interrupts use different save/restore register pairs. This is because the critical class