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MSR
Machine State Register
PPC440x5 CPU Core User’s Manual Preliminary
Page 504 of 589
regsumm440core.fm.
September 12, 2002
MSR
Supervisor R/W
See Machine State Register (MSR) on page 165.
Figure 10-37. Machine State Register (MSR)
0:12 Reserved
13 WE
Wait State Enable
0 The processor is not in the wait state.
1 The processor is in the wait state.
If MSR[WE] = 1, the processor remains in the wait
state until an interrupt is taken, a reset occurs, or
an external debug tool clears WE.
14 CE
Critical Interrupt Enable
0 Critical Input and Watchdog Timer interrupts are
disabled.
1 Critical Input and Watchdog Timer interrupts are
enabled.
15 Reserved
16 EE
External Interrupt Enable
0 External Input, Decrementer, and Fixed Interval
Timer interrupts are disabled.
1 External Input, Decrementer, and Fixed Interval
Timer interrupts are enabled.
17 PR
Problem State
0 Supervisor state (privileged instructions can be
executed)
1 Problem state (privileged instructions can not be
executed)
18 FP
Floating Point Available
0 The processor cannot execute floating-point
instructions
1 The processor can execute floating-point
instructions
19 ME
Machine Check Enable
0 Machine Check interrupts are disabled
1 Machine Check interrupts are enabled.
20 FE0
Floating-point exception mode 0
0 If MSR[FE1] = 0, ignore exceptions mode; if
MSR[FE1] = 1, imprecise nonrecoverable mode
1 If MSR[FE1] = 0, imprecise recoverable mode; if
MSR[FE1] = 1, precise mode
21 DWE
Debug Wait Enable
0 Disable debug wait mode.
1 Enable debug wait mode.
22 DE
Debug interrupt Enable
0 Debug interrupts are disabled.
1 Debug interrupts are enabled.
0 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 31
FE1
WE
PR
DS
CE
EE
DE
FP
ME
DWE
FE0
IS