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User’s Manual
Preliminary PPC440x5 CPU Core
intrupts.fm.
September 12, 2002
Page 179 of 589
tion, regardless of the state of the MSR[ME] bit.
If MSR[ME] is 1 when the Instruction Machine Check exception is presented to the interrupt
mechanism, then execution of the instruction associated with the exception will be sup-
pressed, a Machine Check interrupt will occur, and the interrupt processing registers will be
updated as described on Page 179. If MSR[ME] is 0, however, then the instruction associ-
ated with the exception will be processed as though the exception did not exist and a
Machine Check interrupt will not occur (ever, even if and when MSR[ME] is subsequently set
to 1), although the ESR will still be updated as described on Page 179.
Instruction Asynchronous Machine Check exception
An Instruction Asynchronous Machine Check exception is caused when either:
• an instruction cache parity error is detected
• the read interrupt request is asserted on the instruction read PLB interface.
Data Asynchronous Machine Check exception
A Data Asynchronous Machine Check exception is caused when one of the following occurs:
• a timeout, read error, or read interrupt request is signaled on the data read PLB interface, during a
data read operation
• a timeout, write error, or write interrupt request is signaled on the data write PLB interface, during a
data write operation
• a parity error is detected on an access to the data cache.
TLB Asynchronous Machine Check exception
A TLB Asynchronous Machine Check exception is caused when a parity error is detected on an access to
the TLB.
When any Machine Check exception which is handled as an asynchronous interrupt occurs, it is immediately
presented to the interrupt handling mechanism. MCSR[MCS] is set, as are other bits of the MCSR as appro-
priate. A Machine Check interrupt will occur immediately if MSR[ME] is 1, and the interrupt processing regis-
ters will be updated as described below. If MSR[ME] is 0, however, then the exception will be “recorded” by
the setting of the MCSR[MCS] bit, and deferred until such time as MSR[ME] is subsequently set to 1. Any
time the MCSR[MCS] and MSR[ME] are both set to 1, the Machine Check interrupt will be taken. Therefore,
MCSR[MCS] must be cleared by software in the Machine Check interrupt handler before executing an rfmci
to return to processing with MSR[ME] set to 1.
When a Machine Check interrupt occurs, the interrupt processing registers are updated as indicated below
(all registers not listed are unchanged), and instruction execution resumes at address IVPR[IVP] ||
IVOR1[IVO] || 0b0000.
Machine Check Save/Restore Register 0 (MCSRR0)
For an Instruction Synchronous Machine Check exception, set to the effective address of the
instruction presenting the exception. For an Instruction Asynchronous Machine Check, Data
Asynchronous Machine Check, or TLB Asynchronous Machine Check exception, set to the
effective address of the next instruction to be executed.