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stwcx.
Store Word Conditional Indexed
Preliminary PPC440x5 CPU Core User’s Manual
instrset.fm.
September 12, 2002 Page 425 of 589
The PowerPC Book-E architecture also specifies that it is implementation-dependent as to whether a Data
Storage, Data TLB Error, Alignment, or Debug interrupt occurs when the reservation bit is off at the time of
execution of an stwcx. instruction, and when the conditions are such that a non-stwcx. store-type storage
access instruction would have resulted in such an interrupt. The PPC440x5 implements
stwcx. such that
Data Storage and Debug (DAC and/or DVC exception type) interrupts do not occur when the reservation bit is
off at the time of execution of the
stwcx. Instead, the stwcx. instruction completes without causing the inter-
rupt and without storing to memory, and CR[CR0] is updated to indicate the failure of the stwcx.
On the other hand, the PPC440x5 causes a Data TLB Error interrupt if a Data TLB Miss exception occurs
during due to the execution of a
stwcx. instruction, regardless of the state of the reservation. Similarly, the
PPC440x5 causes an Alignment interrupt if the EA of the
stwcx. operand is not word-aligned when
CCR0[FLSTA] is 1, regardless of the state of the reservation (see Core Configuration Register 0 (CCR0) on
page 108 for more information on the Force Load/Store Alignment function).