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User’s Manual
PPC440x5 CPU Core Preliminary
Page 236 of 589
debug.fm.
September 12, 2002
that there is a special case of MSR[DE] = 1 at the time of the execution of the instruction causing the ICMP
debug event, but that instruction itself sets MSR[DE] to 0. This special case is described in more detail in
Debug Interrupt on page 195, in the subsection on the setting of CSRR0.
When operating in internal debug mode (and not also in external debug mode nor debug wait mode) with
Debug interrupts disabled (MSR[DE] = 0), then ICMP debug events cannot occur. Since the code at the
beginning of the critical class interrupt handlers (including the Debug interrupt itself) must execute at least
temporarily with MSR[DE] = 0, there would be no way to avoid causing additional ICMP debug events and
setting DBSR[IDE], if ICMP debug events were allowed to occur under these conditions.
The PPC440x5 does not support the use of the ICMP debug event when operating in trace mode. Software
must not enable ICMP debug events unless one of the other debug modes is enabled as well.
8.3.8 Interrupt (IRPT) Debug Event
IRPT debug events occur when IRPT debug events are enabled (DBCR0[IRPT] = 1) and an interrupt occurs.
When operating in external debug mode or debug wait mode, the occurrence of an IRPT debug event is
recorded in DBSR[IRPT] and causes the processor to enter the stop state and cease processing instructions.
The program counter will contain the address of the instruction which would have executed next, had the
IRPT debug event not occurred. Since the IRPT debug event is caused by the occurrence of an interrupt, by
definition this address is that of the first instruction of the interrupt handler for the interrupt type which caused
the IRPT debug event.
When operating in internal debug mode with external debug mode and debug wait mode both disabled (and
regardless of the value of MSR[DE]), an IRPT debug event can only occur due to a non-critical class interrupt.
Critical class interrupts (Machine Check, Critical Input, Watchdog Timer, and Debug interrupts) cannot cause
IRPT debug events in internal debug mode (unless also in external debug mode or debug wait mode), as
otherwise the Debug interrupt which would occur as the result of the IRPT debug event would by necessity
always be imprecise, since the critical class interrupt which would be causing the IRPT debug event would
itself be causing MSR[DE] to be set to 0.
For a non-critical class interrupt which is causing an IRPT debug event while internal debug mode is enabled
and external debug mode and debug wait mode are both disabled, the occurrence of the IRPT debug event is
recorded in DBSR[IRPT]. If MSR[DE] is 1 at the time of the IRPT debug event, then a Debug interrupt occurs
with CSRR0 set to the address of the instruction which would have executed next, had the IRPT debug event
not occurred. Since the IRPT debug event is caused by the occurrence of some other interrupt, by definition
this address is that of the first instruction of the interrupt handler for the interrupt type which caused the IRPT
debug event. If MSR[DE] is 0 at the time of the IRPT debug event, then the Imprecise Debug Event (IDE) field
of the DBSR is also set and a Debug interrupt does not occur immediately. Instead, instruction execution
continues, and a Debug interrupt will occur if and when MSR[DE] is set to 1, thereby enabling Debug inter-
rupts, assuming software has not cleared the IRPT debug event status from the DBSR in the meantime.
Upon such a “delayed” interrupt, the Debug interrupt handler software may query the DBSR[IDE] field to
determine that the Debug interrupt has occurred imprecisely.
When operating in trace mode, the occurrence of an IRPT debug event is simply recorded in DBSR[IRPT]
and is indicated over the trace interface, and instruction execution continues.