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User’s Manual
PPC440x5 CPU Core Preliminary
Page 520 of 589
instalfa.fm.
September 12, 2002
A.1.1 Instruction Fields
PPC440x5 instructions contain various combinations of the following fields, as indicated in the instruction
format diagrams that follow the field definitions. Numbers, enclosed in parentheses, that follow the field
names indicate bit positions; bit fields are indicated by starting and stopping bit positions separated by
colons.
AA (30) Absolute address bit.
0 The immediate field represents an address relative to the current instruction address
(CIA). The effective address (EA) of the branch is either the sum of the LI field sign-
extended to 32 bits and the branch instruction address, or the sum of the BD field
sign-extended to 32 bits and the branch instruction address.
1 The immediate field represents an absolute address. The EA of the branch is either
the LI field or the BD field, sign-extended to 32 bits.
BA (11:15) Specifies a bit in the CR used as a source of a CR-logical instruction.
BB (16:20) Specifies a bit in the CR used as a source of a CR-logical instruction.
BD (16:29) An immediate field specifying a 14-bit signed twos complement branch displacement.
This field is concatenated on the right with 0b00 and sign-extended to 32 bits.
BF (6:8) Specifies a field in the CR used as a target in a compare or mcrf instruction.
BFA (11:13) Specifies a field in the CR used as a source in a mcrf instruction.
BI (11:15) Specifies a bit in the CR used as a source for the condition of a conditional branch
instruction.
BO (6:10) Specifies options for conditional branch instructions. See Branch Instruction BO Field on
page 64.
BT (6:10) Specifies a bit in the CR used as a target as the result of a CR-Logical instruction.
D (16:31) Specifies a 16-bit signed two’s-complement integer displacement for load/store
instructions.
DCRF (11:20) Specifies a device control register (DCR). This field represents the DCR Number
(DCRN) with the upper and lower five bits reversed (that is,
DCRF = DCRN[5:9] || DCRN[0:4]).
FXM (12:19) Field mask used to identify CR fields to be updated by the mtcrf instruction.
IM (16:31) An immediate field used to specify a 16-bit value (either signed integer or unsigned).
LI (6:29) An immediate field specifying a 24-bit signed twos complement branch displacement;
this field is concatenated on the right with b'00' and sign-extended to 32 bits.
LK (31) Link bit.
0 Do not update the link register (LR).
1 Update the LR with the address of the next instruction.
MB (21:25) Mask begin.
Used in rotate-and-mask instructions to specify the beginning bit of a mask.
ME (26:30) Mask end.