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User’s Manual
Preliminary PPC440x5 CPU Core
ppc440x5LOF.fm.
September 12, 2002
Page 15 of 583
Figures
Figure 1-1. PPC440 Core Block Diagram .................................................................................................30
Figure 2-1. User Programming Model Registers ......................................................................................48
Figure 2-2. Supervisor Programming Model Registers ............................................................................49
Figure 2-3. Link Register (LR) ..................................................................................................................67
Figure 2-4. Count Register (CTR) ............................................................................................................67
Figure 2-5. Condition Register (CR) .........................................................................................................68
Figure 2-6. General Purpose Registers (R0-R31) ....................................................................................71
Figure 2-7. Integer Exception Register (XER) ..........................................................................................72
Figure 2-8. Special Purpose Registers General (USPRG0, SPRG0–SPRG7) ........................................75
Figure 2-9. Processor Version Register (PVR) .........................................................................................76
Figure 2-10. Processor Identification Register (PIR) ..................................................................................76
Figure 2-11. Core Configuration Register 0 (CCR0) ..................................................................................77
Figure 2-12. Core Configuration Register 1 (CCR1) ..................................................................................78
Figure 2-13. Reset Configuration ...............................................................................................................79
Figure 4-1. Instruction Cache Normal Victim Registers (INV0–INV3) ......................................................97
Figure 4-1. Instruction Cache Transient Victim Registers (ITV0–ITV3) ....................................................97
Figure 4-1. Data Cache Normal Victim Registers (DNV0–DNV3) ............................................................97
Figure 4-1. Data Cache Transient Victim Registers (DTV0–DTV3) .........................................................97
Figure 4-2. Instruction Cache Victim Limit (IVLIM) ...................................................................................99
Figure 4-2. Data Cache Victim Limit (DVLIM) ..........................................................................................99
Figure 4-3. Cache Locking and Transient Mechanism (Example 1)1 .....................................................102
Figure 4-4. Cache Locking and Transient Mechanism (Example 2) .......................................................103
Figure 4-5. Core Configuration Register 0 (CCR0) ................................................................................109
Figure 4-6. Core Configuration Register 1 (CCR1) ................................................................................110
Figure 4-7. Instruction Cache Debug Data Register (ICDBDR) .............................................................113
Figure 4-8. Instruction Cache Debug Tag Register High (ICDBTRH) ....................................................113
Figure 4-9. Instruction Cache Debug Tag Register Low (ICDBTRL) ......................................................113
Figure 4-10. Data Cache Debug Tag Register High (DCDBTRH) ............................................................128
Figure 4-11. Data Cache Debug Tag Register Low (DCDBTRL) .............................................................128
Figure 5-1. Virtual Address to TLB Entry Match Process .......................................................................140
Figure 5-2. Effective-to-Real Address Translation Flow .........................................................................141
Figure 5-3. Memory Management Unit Control Register (MMUCR) .......................................................148
Figure 5-4. Process ID (PID) ..................................................................................................................151
Figure 5-5. TLB Entry Word Definitions ..................................................................................................154
Figure 6-1. Machine State Register (MSR) ............................................................................................165
Figure 6-2. Save/Restore Register 0 (SRR0) .........................................................................................167