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User’s Manual
Preliminary PPC440x5 CPU Core
preface.fm.
September 12, 2002
Page 23 of 589
About This Book
This user’s manual provides the architectural overview, programming model, and detailed information about
the instruction set, registers, and other facilities of the IBM™ Book-E Enhanced PowerPC™ 440x5
(PPC440x5™) 32-bit embedded controller core.
The PPC440x5 embedded controller core features:
• Book-E Enhanced PowerPC Architecture™
• Dual-issue superscalar pipeline with dynamic branch prediction
• Separate, configurable (up to 32KB each) instruction and data caches, with cache line locking
• DSP acceleration with 24 new integer multiply-accumulate (MAC) instructions
• Memory Management Unit (MMU) with 64-entry TLB and support for page sizes of 1KB–256MB
• 64GB (36-bit) physical address capability
• 128-bit PLB interface, part of the IBM CoreConnect™ on-chip system bus architecture
• JTAG debug interface with extensive integrated debug facilities, including real-time trace
Who Should Use This Book
This book is for system hardware and software developers, and for application developers who need to
understand the PPC440x5. The audience should understand embedded system design, operating systems,
RISC microprocessing, and computer organization and architecture.
How to Use This Book
This book describes the PPC440x5 device architecture, programming model, registers, and instruction set.
This book contains the following chapters:
Chapter 1. Overview
Chapter 2. Programming Model
Chapter 3. Initialization
Chapter 4. Instruction and Data Caches
Chapter 5. Memory Management
Chapter 6. Interrupts and Exceptions
Chapter 7. Timer Facilities
Chapter 8. Debug Facilities
Chapter 9. Instruction Set
Chapter 10. Register Summary
This book contains the following appendixes:
Appendix A. Instruction Summary
Appendix B. PPC440 Core Compiler Optimizations
Appendix B contains preliminary information.
To help readers find material in these chapters, this book contains: